[PATCH] D46851: [WIP] [AArch64] Pattern-match byte store from a vector register.

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

In https://reviews.llvm.org/D46851#1098587, @efriedma wrote:

> i8 isn't considered a legal type by the AArch64ISelLowering, so it will never show up in the input to the instruction selector. Given that, I'm not sure it's really meaningful to say i8 maps to any specific register class.
>
> But I guess it wouldn't do any harm to list i8 as part of FPR8?  At least, I can't think of any other effects.


I'll give it a shot, hoping that I won't go down a rabbit hole...


Repository:
  rL LLVM

https://reviews.llvm.org/D46851