[PATCH] D43441: [X86][AVX512DQ] Use packed instructions for scalar FP<->i64 conversions on 32-bit targets (PR31630)

[Elena Demikhovsky via Phabricator via llvm-commits]

delena added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:16065
 
+  // Pack the i64 into a vector, do the operation and extract.
+  if (Subtarget.hasDQI() && isScalarFPTypeInSSEReg(VT) &&
----------------
This case is the same for SINT and UINT. May be put them in a function?


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:25275
+      MVT VecVT = Subtarget.hasVLX() ? MVT::v4i64 : MVT::v8i64;
+      MVT VecInVT = MVT::getVectorVT(SrcVT.getSimpleVT(), NumElts);
+
----------------
VecVT =  MVT::getVectorVT(VT, NumElts);


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:25279
+      SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecInVT,
+                                DAG.getConstantFP(0.0, dl, VecInVT),
+                                Src, ZeroIdx);
----------------
Why do you need to insert into zero vector? Can you insert to undef?


================
Comment at: test/CodeGen/X86/scalar-fp-to-i64.ll:541
+; AVX512DQVL_32_LIN:       # %bb.0:
+; AVX512DQVL_32_LIN-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
+; AVX512DQVL_32_LIN-NEXT:    vcvttpd2uqq %ymm0, %ymm0
----------------
Can the memory operand be folded here?
VCVTTPD2UQQ ymm1 {k1}{z},ymm2/m256/**m64bcst**


https://reviews.llvm.org/D43441