[llvm] r332260 - [Hexagon] Avoid predicate copies to integer registers from store-locked
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon May 14 09:41:40 PDT 2018
Author: kparzysz
Date: Mon May 14 09:41:40 2018
New Revision: 332260
URL: http://llvm.org/viewvc/llvm-project?rev=332260&view=rev
Log:
[Hexagon] Avoid predicate copies to integer registers from store-locked
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll
llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll
llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=332260&r1=332259&r2=332260&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Mon May 14 09:41:40 2018
@@ -2910,3 +2910,18 @@ def HexagonREADCYCLE: SDNode<"HexagonISD
[SDNPHasChain]>;
def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>;
+
+// The declared return value of the store-locked intrinsics is i32, but
+// the instructions actually define i1. To avoid register copies from
+// IntRegs to PredRegs and back, fold the entire pattern checking the
+// result against true/false.
+let AddedComplexity = 100 in {
+ def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)),
+ (S2_storew_locked I32:$Rs, I32:$Rt)>;
+ def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)),
+ (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>;
+ def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)),
+ (S4_stored_locked I32:$Rs, I64:$Rt)>;
+ def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)),
+ (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>;
+}
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll?rev=332260&r1=332259&r2=332260&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll Mon May 14 09:41:40 2018
@@ -39,7 +39,7 @@ BINARY_OP_entry:
; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memw(gp+#i32Result) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
@@ -60,7 +60,7 @@ entry:
; CHECK: [[RESULT_REG:r[0-9]+:[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memd(gp+#i64Result) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
@@ -81,7 +81,7 @@ entry:
; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memw(gp+#ptrResult) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll?rev=332260&r1=332259&r2=332260&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll Mon May 14 09:41:40 2018
@@ -32,7 +32,7 @@
; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memw(gp+#g2) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
define void @f0() {
@@ -53,7 +53,7 @@ BINARY_OP_entry:
; CHECK: [[RESULT_REG:r[:0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memd(gp+#g5) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
define void @f1() {
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll?rev=332260&r1=332259&r2=332260&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll Mon May 14 09:41:40 2018
@@ -22,7 +22,7 @@
; CHECK: [[RESULT_REG:r[0-9]+]] = sub(#-1,[[AND_RESULT_REG]])
; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memw(gp+#g2) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
define void @f0() {
@@ -44,7 +44,7 @@ b0:
; CHECK: [[RESULT_REG:r[:0-9]+]] = not([[AND_RESULT_REG]])
; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memd(gp+#g5) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
define void @f1() {
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