[PATCH] D46536: [Power9]Legalize and emit code for W vector extract and convert to Quad-Precision

[Lei Huang via Phabricator via llvm-commits]

lei marked 3 inline comments as done.
lei added inline comments.


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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:3167
+    // (Un)Signed Word vector extract -> QP
+    def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 0)))),
+              (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;
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nemanjai wrote:
> It is actually word 1 that doesn't need the splat. Word 0 does need a splat.
You are right!


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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:3196
+    // (Un)Signed Word vector extract -> QP
+    foreach Idx = [[0,3],[1,2],[2,1]] in {
+      def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),
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nemanjai wrote:
> This should actually be `foreach Idx = [[0,3],[1,2],[3,0]]` shouldn't it? For LE word element 2, `VEXTSW2D` will sign extend it into LE doubleword element 1 which is where `XSCVSDQP` needs it to be - so a splat is not needed. LE word element 3 on the other hand **will** need a splat since the input is in the left half of LE doubleword 1 and it needs to be in the right half.
Yes. This is true... I forgot to check this when I switched `xvcvsxwdp` for `vextsw2d`.


https://reviews.llvm.org/D46536