[llvm] r332191 - [NFC] MIR-Canon: switching to a stable string sorting of instructions.

[Puyan Lotfi via llvm-commits]

Author: zer0
Date: Sat May 12 23:07:20 2018
New Revision: 332191

URL: http://llvm.org/viewvc/llvm-project?rev=332191&view=rev
Log:
[NFC] MIR-Canon: switching to a stable string sorting of instructions.

Modified:
    llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
    llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir

Modified: llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp?rev=332191&r1=332190&r2=332191&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp Sat May 12 23:07:20 2018
@@ -120,7 +120,8 @@ rescheduleLexographically(std::vector<Ma
                           std::function<MachineBasicBlock::iterator()> getPos) {
 
   bool Changed = false;
-  std::map<std::string, MachineInstr *> StringInstrMap;
+  using StringInstrPair = std::pair<std::string, MachineInstr *>;
+  std::vector<StringInstrPair> StringInstrMap;
 
   for (auto *II : instructions) {
     std::string S;
@@ -130,9 +131,14 @@ rescheduleLexographically(std::vector<Ma
 
     // Trim the assignment, or start from the begining in the case of a store.
     const size_t i = S.find("=");
-    StringInstrMap.insert({(i == std::string::npos) ? S : S.substr(i), II});
+    StringInstrMap.push_back({(i == std::string::npos) ? S : S.substr(i), II});
   }
 
+  std::sort(StringInstrMap.begin(), StringInstrMap.end(),
+            [](StringInstrPair &a, StringInstrPair &b) {
+              return (a.first < b.first);
+            });
+
   for (auto &II : StringInstrMap) {
 
     DEBUG({

Modified: llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir?rev=332191&r1=332190&r2=332191&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir Sat May 12 23:07:20 2018
@@ -2,9 +2,10 @@
 # These Idempotent instructions are sorted alphabetically (based on after the '=')
 # CHECK: %namedVReg4352:gpr64 = MOVi64imm 4617315517961601024
 # CHECK: %namedVReg4353:gpr32 = MOVi32imm 408
-# CHECK: %namedVReg4354:gpr64all = IMPLICIT_DEF
-# CHECK: %namedVReg4355:fpr64 = FMOVDi 20
-# CHECK: %namedVReg4356:fpr64 = FMOVDi 112
+# CHECK: %namedVReg4354:gpr32 = MOVi32imm 408
+# CHECK: %namedVReg4355:gpr64all = IMPLICIT_DEF
+# CHECK: %namedVReg4356:fpr64 = FMOVDi 20
+# CHECK: %namedVReg4357:fpr64 = FMOVDi 112
 ...
 ---
 name: Proc8