[llvm] r332082 - AMDGPU/GlobalISel: Implement select() for 32-bit G_FPTOUI
Tom Stellard via llvm-commits
llvm-commits at lists.llvm.org
Thu May 10 22:44:16 PDT 2018
Author: tstellar
Date: Thu May 10 22:44:16 2018
New Revision: 332082
URL: http://llvm.org/viewvc/llvm-project?rev=332082&view=rev
Log:
AMDGPU/GlobalISel: Implement select() for 32-bit G_FPTOUI
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45883
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td?rev=332082&r1=332081&r2=332082&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td Thu May 10 22:44:16 2018
@@ -18,6 +18,10 @@ def gi_vsrc0 :
GIComplexOperandMatcher<s32, "selectVSRC0">,
GIComplexPatternEquiv<sd_vsrc0>;
+def gi_vop3mods0 :
+ GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
+ GIComplexPatternEquiv<VOP3Mods0>;
+
class GISelSop2Pat <
SDPatternOperator node,
Instruction inst,
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=332082&r1=332081&r2=332082&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Thu May 10 22:44:16 2018
@@ -455,6 +455,7 @@ bool AMDGPUInstructionSelector::select(M
switch (I.getOpcode()) {
default:
break;
+ case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_OR:
return selectImpl(I, CoverageInfo);
case TargetOpcode::G_ADD:
@@ -482,3 +483,13 @@ AMDGPUInstructionSelector::selectVSRC0(M
[=](MachineInstrBuilder &MIB) { MIB.add(Root); }
}};
}
+
+InstructionSelector::ComplexRendererFns
+AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
+ return {{
+ [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
+ [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src0_mods
+ [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
+ [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
+ }};
+}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h?rev=332082&r1=332081&r2=332082&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h Thu May 10 22:44:16 2018
@@ -73,6 +73,9 @@ private:
InstructionSelector::ComplexRendererFns
selectVSRC0(MachineOperand &Root) const;
+ InstructionSelector::ComplexRendererFns
+ selectVOP3Mods0(MachineOperand &Root) const;
+
const SIInstrInfo &TII;
const SIRegisterInfo &TRI;
const AMDGPURegisterBankInfo &RBI;
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir?rev=332082&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir Thu May 10 22:44:16 2018
@@ -0,0 +1,36 @@
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+
+--- |
+ define amdgpu_kernel void @fptoui(i32 addrspace(1)* %global0) {ret void}
+...
+---
+
+name: fptoui
+legalized: true
+regBankSelected: true
+
+# GCN-LABEL: name: fptoui
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
+
+ ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ %0:sgpr(s32) = COPY $sgpr0
+
+ ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr0
+
+ %2:vgpr(s64) = COPY $vgpr3_vgpr4
+
+ ; fptoui s
+ ; GCN: V_CVT_U32_F32_e64 0, [[SGPR]], 0, 0
+ %3:vgpr(s32) = G_FPTOUI %0
+
+ ; fptoui v
+ ; GCN: V_CVT_U32_F32_e64 0, [[VGPR]], 0, 0
+ %4:vgpr(s32) = G_FPTOUI %1
+
+ G_STORE %3, %2 :: (store 4 into %ir.global0)
+ G_STORE %4, %2 :: (store 4 into %ir.global0)
+...
+---
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