[llvm] r331969 - [mips] Correct the predicates of cvt.fmt.fmt instructions
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Thu May 10 03:42:30 PDT 2018
Author: sdardis
Date: Thu May 10 03:42:30 2018
New Revision: 331969
URL: http://llvm.org/viewvc/llvm-project?rev=331969&view=rev
Log:
[mips] Correct the predicates of cvt.fmt.fmt instructions
Reviewers: atanasyan, smaksimovic, abeserminji
Differential Revision: https://reviews.llvm.org/D46390
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt
llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s
llvm/trunk/test/MC/Mips/micromips/valid-fp64.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r3/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Thu May 10 03:42:30 2018
@@ -77,11 +77,11 @@ let DecoderNamespace = "MicroMips" in {
BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6;
def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6;
+ def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
+ ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS;
}
let isCodeGenOnly = 1 in {
-def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
- ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS;
def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd,
II_ROUND>, ROUND_W_FM_MM<0, 0xec>,
ISA_MICROMIPS;
@@ -95,13 +95,13 @@ def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS
ISA_MICROMIPS, FGR_32;
def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32;
-def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
- ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64;
-def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
- ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64;
-
}
let DecoderNamespace = "MicroMips" in {
+ def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
+ ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64;
+ def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
+ ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64;
+
def CVT_W_D32_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32;
}
@@ -155,10 +155,10 @@ let DecoderNamespace = "MicroMipsFP64" i
let DecoderNamespace = "MicroMips" in {
def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32;
+ def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
+ ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS;
}
-def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
- ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS;
defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Thu May 10 03:42:30 2018
@@ -358,14 +358,15 @@ def CEIL_W_S : MMRel, StdMMR6Rel, ABSS
ABSS_FM<0xe, 16>, ISA_MIPS2;
def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
ABSS_FM<0xf, 16>, ISA_MIPS2;
-def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
- ABSS_FM<0x24, 16>;
+let AdditionalPredicates = [NotInMicroMips] in
+ def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
+ ABSS_FM<0x24, 16>, ISA_MIPS1;
defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
let AdditionalPredicates = [NotInMicroMips] in {
- defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
+ defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1;
}
let AdditionalPredicates = [NotInMicroMips] in {
@@ -411,9 +412,9 @@ let DecoderNamespace = "MipsFP64" in {
}
}
-def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
- ABSS_FM<0x20, 20>;
let AdditionalPredicates = [NotInMicroMips] in{
+ def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
+ ABSS_FM<0x20, 20>, ISA_MIPS1;
def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
@@ -422,25 +423,25 @@ let AdditionalPredicates = [NotInMicroMi
let AdditionalPredicates = [NotInMicroMips] in {
def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
- ABSS_FM<0x20, 17>, FGR_32;
+ ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32;
def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
- ABSS_FM<0x21, 16>, FGR_32;
+ ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32;
def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
- ABSS_FM<0x21, 20>, FGR_32;
+ ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32;
}
let DecoderNamespace = "MipsFP64" in {
let AdditionalPredicates = [NotInMicroMips] in {
def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
- ABSS_FM<0x20, 21>, FGR_64;
+ ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64;
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
- ABSS_FM<0x20, 17>, FGR_64;
+ ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64;
def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
- ABSS_FM<0x21, 20>, FGR_64;
+ ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64;
def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
- ABSS_FM<0x21, 16>, FGR_64;
+ ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64;
+ def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
+ ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_64;
}
- def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
- ABSS_FM<0x21, 21>, FGR_64;
}
let isPseudo = 1, isCodeGenOnly = 1 in {
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt Thu May 10 03:42:30 2018
@@ -17,3 +17,5 @@
0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2
0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
+0x82 0x54 0x3b 0x01 # CHECK: cvt.l.s $f4, $f2
+0x82 0x54 0x3b 0x41 # CHECK: cvt.l.d $f4, $f2
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt Thu May 10 03:42:30 2018
@@ -17,3 +17,5 @@
0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2
0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2
0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2
+0x54 0x82 0x01 0x3b # CHECK: cvt.l.s $f4, $f2
+0x54 0x82 0x41 0x3b # CHECK: cvt.l.d $f4, $f2
Modified: llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s Thu May 10 03:42:30 2018
@@ -46,10 +46,13 @@
# CHECK-EL: neg.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x0b]
# CHECK-EL: neg.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x2b]
# CHECK-EL: cvt.d.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x13]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S_MM
# CHECK-EL: cvt.d.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x33]
-# CHECK-EL: # <MCInst #{{.*}} CVT_D32_W_MM
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W_MM
# CHECK-EL: cvt.s.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x1b]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32_MM
# CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_S_W_MM
# CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10]
# CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18]
# CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20]
@@ -120,10 +123,13 @@
# CHECK-EB: neg.s $f6, $f8 # encoding: [0x54,0xc8,0x0b,0x7b]
# CHECK-EB: neg.d $f6, $f8 # encoding: [0x54,0xc8,0x2b,0x7b]
# CHECK-EB: cvt.d.s $f6, $f8 # encoding: [0x54,0xc8,0x13,0x7b]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S_MM
# CHECK-EB: cvt.d.w $f6, $f8 # encoding: [0x54,0xc8,0x33,0x7b]
-# CHECK-EB: # <MCInst #{{.*}} CVT_D32_W_MM
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W_MM
# CHECK-EB: cvt.s.d $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x7b]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32_MM
# CHECK-EB: cvt.s.w $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x7b]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_S_W_MM
# CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b]
# CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b]
# CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b]
Modified: llvm/trunk/test/MC/Mips/micromips/valid-fp64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/valid-fp64.s?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/valid-fp64.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/valid-fp64.s Thu May 10 03:42:30 2018
@@ -15,6 +15,10 @@ cvt.s.d $f0, $f2 # CHECK: cvt.s.d $
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64_MM
cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x54,0x02,0x49,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64_MM
+cvt.l.s $f4, $f2 # CHECK: cvt.l.s $f4, $f2 # encoding: [0x54,0x82,0x01,0x3b]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_L_S_MM
+cvt.l.d $f4, $f2 # CHECK: cvt.l.d $f4, $f2 # encoding: [0x54,0x82,0x41,0x3b]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_L_D64_MM
div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64_MM
mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x54,0x80,0x30,0x3b]
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Thu May 10 03:42:30 2018
@@ -47,16 +47,26 @@ a:
ceil.w.s $f6,$f20
cfc1 $s1,$21
ctc1 $a2,$26
- cvt.d.l $f4,$f16
- cvt.d.s $f22,$f28
- cvt.d.w $f26,$f11
- cvt.l.d $f24,$f15
- cvt.l.s $f11,$f29
- cvt.s.d $f26,$f8
- cvt.s.l $f15,$f30
- cvt.s.w $f22,$f15
- cvt.w.d $f20,$f14
- cvt.w.s $f20,$f24
+ cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
+ cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
+ cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
+ cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
+ cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
+ cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
+ cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
+ cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
+ cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
+ cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Thu May 10 03:42:30 2018
@@ -79,16 +79,26 @@ a:
ceil.w.s $f6,$f20
cfc1 $s1,$21
ctc1 $a2,$26
- cvt.d.l $f4,$f16
- cvt.d.s $f22,$f28
- cvt.d.w $f26,$f11
- cvt.l.d $f24,$f15
- cvt.l.s $f11,$f29
- cvt.s.d $f26,$f8
- cvt.s.l $f15,$f30
- cvt.s.w $f22,$f15
- cvt.w.d $f20,$f14
- cvt.w.s $f20,$f24
+ cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
+ cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
+ cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
+ cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
+ cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
+ cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
+ cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
+ cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
+ cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
+ cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Thu May 10 03:42:30 2018
@@ -79,16 +79,26 @@ a:
ceil.w.s $f6,$f20
cfc1 $s1,$21
ctc1 $a2,$26
- cvt.d.l $f4,$f16
- cvt.d.s $f22,$f28
- cvt.d.w $f26,$f11
- cvt.l.d $f24,$f15
- cvt.l.s $f11,$f29
- cvt.s.d $f26,$f8
- cvt.s.l $f15,$f30
- cvt.s.w $f22,$f15
- cvt.w.d $f20,$f14
- cvt.w.s $f20,$f24
+ cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
+ cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
+ cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
+ cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
+ cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
+ cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
+ cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
+ cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
+ cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
+ cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Thu May 10 03:42:30 2018
@@ -81,16 +81,26 @@ a:
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26
- cvt.d.l $f4,$f16
- cvt.d.s $f22,$f28
- cvt.d.w $f26,$f11
- cvt.l.d $f24,$f15
- cvt.l.s $f11,$f29
- cvt.s.d $f26,$f8
- cvt.s.l $f15,$f30
- cvt.s.w $f22,$f15
- cvt.w.d $f20,$f14
- cvt.w.s $f20,$f24
+ cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
+ cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
+ cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
+ cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
+ cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
+ cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
+ cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
+ cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
+ cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
+ cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Thu May 10 03:42:30 2018
@@ -81,16 +81,26 @@ a:
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26
- cvt.d.l $f4,$f16
- cvt.d.s $f22,$f28
- cvt.d.w $f26,$f11
- cvt.l.d $f24,$f15
- cvt.l.s $f11,$f29
- cvt.s.d $f26,$f8
- cvt.s.l $f15,$f30
- cvt.s.w $f22,$f15
- cvt.w.d $f20,$f14
- cvt.w.s $f20,$f24
+ cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
+ cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
+ cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
+ cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
+ cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
+ cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
+ cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
+ cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
+ cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
+ cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid.s?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s Thu May 10 03:42:30 2018
@@ -81,16 +81,26 @@ a:
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26
- cvt.d.l $f4,$f16
- cvt.d.s $f22,$f28
- cvt.d.w $f26,$f11
- cvt.l.d $f24,$f15
- cvt.l.s $f11,$f29
- cvt.s.d $f26,$f8
- cvt.s.l $f15,$f30
- cvt.s.w $f22,$f15
- cvt.w.d $f20,$f14
- cvt.w.s $f20,$f24
+ cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
+ cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
+ cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
+ cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
+ cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
+ cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
+ cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
+ cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
+ cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
+ cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=331969&r1=331968&r2=331969&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Thu May 10 03:42:30 2018
@@ -81,16 +81,26 @@ a:
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26
- cvt.d.l $f4,$f16
- cvt.d.s $f22,$f28
- cvt.d.w $f26,$f11
- cvt.l.d $f24,$f15
- cvt.l.s $f11,$f29
- cvt.s.d $f26,$f8
- cvt.s.l $f15,$f30
- cvt.s.w $f22,$f15
- cvt.w.d $f20,$f14
- cvt.w.s $f20,$f24
+ cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
+ cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
+ cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
+ cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
+ cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
+ cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
+ cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
+ cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
+ cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
+ cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
+ # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
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