[PATCH] D46179: [X86] Lowering adds/addus/subs/subus intrinsics to native IR (LLVM part)

[Tomasz Krupa via Phabricator via llvm-commits]

tkrupa added a comment.

About test/CodeGen/X86/avx2-intrinsics-fast-isel.ll change - there is a canonical form for subus pattern I'm using here - it's different from adds/addus/subs patterns. While those three use ext/trunc pattern and fold correctly, subus has only max+sub. If fast-isel is enabled, sub is not put into SelectionDAG - that's what prevents it from combining. Instead, it's appended as an appropriate after isel as a lowered node. Is there a machine instruction pass for combining?


Repository:
  rL LLVM

https://reviews.llvm.org/D46179