[PATCH] D46677: [RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos.
Herald added subscribers: llvm-commits, mgrang, edward-jones, zzheng, shiva0217, niosHD, sabuasal, jordy.potman.lists, simoncook, johnrusso, rbar.

Add R_RISCV_RELAX relocation to all possible relax candidates and corresponding testcase.


Repository:
  rL LLVM

https://reviews.llvm.org/D46677

Files:
  lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  test/MC/RISCV/linker-relaxation.s


Index: test/MC/RISCV/linker-relaxation.s
===================================================================
--- test/MC/RISCV/linker-relaxation.s
+++ test/MC/RISCV/linker-relaxation.s
@@ -12,3 +12,27 @@
 # RELAX-RELOC: R_RISCV_RELAX foo 0x0
 beq s1, s1, .L1
 # RELAX-RELOC: R_RISCV_BRANCH .L1 0x0
+
+lui t1, %hi(foo)
+# RELOC: R_RISCV_HI20 foo 0x0
+# RELAX-RELOC: R_RISCV_RELAX foo 0x0
+
+addi t1, t1, %lo(foo)
+# RELOC: R_RISCV_LO12_I foo 0x0
+# RELAX-RELOC: R_RISCV_RELAX foo 0x0
+
+sb t1, %lo(foo)(a2)
+# RELOC: R_RISCV_LO12_S foo 0x0
+# RELAX-RELOC: R_RISCV_RELAX foo 0x0
+
+auipc t1, %pcrel_hi(foo)
+# RELOC: R_RISCV_PCREL_HI20 foo 0x0
+# RELAX-RELOC: R_RISCV_RELAX foo 0x0
+
+addi t1, t1, %pcrel_lo(foo)
+# RELOC: R_RISCV_PCREL_LO12_I foo 0x0
+# RELAX-RELOC: R_RISCV_RELAX foo 0x0
+
+sb t1, %pcrel_lo(foo)(a2)
+# RELOC: R_RISCV_PCREL_LO12_S foo 0x0
+# RELAX-RELOC: R_RISCV_RELAX foo 0x0
Index: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -190,6 +190,7 @@
 
   MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
   unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask;
+  bool RelaxCandidate = false;
 
   // If the destination is an immediate, there is nothing to do
   if (MO.isImm())
@@ -214,9 +215,11 @@
         FixupKind = RISCV::fixup_riscv_lo12_s;
       else
         llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
+      RelaxCandidate = true;
       break;
     case RISCVMCExpr::VK_RISCV_HI:
       FixupKind = RISCV::fixup_riscv_hi20;
+      RelaxCandidate = true;
       break;
     case RISCVMCExpr::VK_RISCV_PCREL_LO:
       if (MIFrm == RISCVII::InstFormatI)
@@ -226,12 +229,15 @@
       else
         llvm_unreachable(
             "VK_RISCV_PCREL_LO used with unexpected instruction format");
+      RelaxCandidate = true;
       break;
     case RISCVMCExpr::VK_RISCV_PCREL_HI:
       FixupKind = RISCV::fixup_riscv_pcrel_hi20;
+      RelaxCandidate = true;
       break;
     case RISCVMCExpr::VK_RISCV_CALL:
       FixupKind = RISCV::fixup_riscv_call;
+      RelaxCandidate = true;
       break;
     }
   } else if (Kind == MCExpr::SymbolRef &&
@@ -253,13 +259,11 @@
       MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
   ++MCNumFixups;
 
-  if (EnableRelax) {
-    if (FixupKind == RISCV::fixup_riscv_call) {
-      Fixups.push_back(
-      MCFixup::create(0, Expr, MCFixupKind(RISCV::fixup_riscv_relax),
-                      MI.getLoc()));
-      ++MCNumFixups;
-    }
+  if (EnableRelax && RelaxCandidate) {
+    Fixups.push_back(
+    MCFixup::create(0, Expr, MCFixupKind(RISCV::fixup_riscv_relax),
+                    MI.getLoc()));
+    ++MCNumFixups;
   }
 
   return 0;


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