[PATCH] D44886: [RISCV] Support linker relax function call from auipc and jalr to jal

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 updated this revision to Diff 146071.
shiva0217 edited the summary of this revision.
shiva0217 added a comment.

Split ShouldForceRelocation+FeatureRelax into a sperate patch for better structure patches as Alex's suggestion.


Repository:
  rL LLVM

https://reviews.llvm.org/D44886

Files:
  lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
  lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  test/MC/RISCV/linker-relaxation.s


Index: test/MC/RISCV/linker-relaxation.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/linker-relaxation.s
@@ -0,0 +1,14 @@
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s \
+# RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELAX-RELOC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \
+# RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
+
+.long foo
+
+.L1:
+call foo
+# RELOC: R_RISCV_CALL foo 0x0
+# RELAX-RELOC: R_RISCV_CALL foo 0x0
+# RELAX-RELOC: R_RISCV_RELAX foo 0x0
+beq s1, s1, .L1
+# RELAX-RELOC: R_RISCV_BRANCH .L1 0x0
Index: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -185,7 +185,7 @@
 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
-
+  bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
   const MCOperand &MO = MI.getOperand(OpNo);
 
   MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
@@ -253,6 +253,15 @@
       MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
   ++MCNumFixups;
 
+  if (EnableRelax) {
+    if (FixupKind == RISCV::fixup_riscv_call) {
+      Fixups.push_back(
+      MCFixup::create(0, Expr, MCFixupKind(RISCV::fixup_riscv_relax),
+                      MI.getLoc()));
+      ++MCNumFixups;
+    }
+  }
+
   return 0;
 }
 
Index: lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
+++ lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
@@ -50,6 +50,9 @@
   // fixup_riscv_call - A fixup representing a call attached to the auipc
   // instruction in a pair composed of adjacent auipc+jalr instructions.
   fixup_riscv_call,
+  // fixup_riscv_relax - Used to generate an R_RISCV_RELAX relocation type,
+  // which indicates the linker may relax the instruction pair.
+  fixup_riscv_relax,
 
   // fixup_riscv_invalid - used as a sentinel and a marker, must be last fixup
   fixup_riscv_invalid,
Index: lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
+++ lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
@@ -78,6 +78,8 @@
     return ELF::R_RISCV_RVC_BRANCH;
   case RISCV::fixup_riscv_call:
     return ELF::R_RISCV_CALL;
+  case RISCV::fixup_riscv_relax:
+    return ELF::R_RISCV_RELAX;
   }
 }
 


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