[PATCH] D46655: [AArch64] Improve single vector lane stores

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/arm64-st1.ll:51
+; CHECK-LABEL: st1lane0u_8h
+; CHECK-NOT: str
+  %ptr = getelementptr i16, i16* %D, i64 -1
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Please don't use CHECK-NOT like this; it isn't clear what we're actually generating.


https://reviews.llvm.org/D46655