[llvm] r331913 - [X86] Fix Broadwell's Shuffle256 schedule classes load latency values.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed May 9 12:27:48 PDT 2018
Author: rksimon
Date: Wed May 9 12:27:48 2018
New Revision: 331913
URL: http://llvm.org/viewvc/llvm-project?rev=331913&view=rev
Log:
[X86] Fix Broadwell's Shuffle256 schedule classes load latency values.
Allows us to remove some unnecessary InstRW overrides.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=331913&r1=331912&r2=331913&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Wed May 9 12:27:48 2018
@@ -423,10 +423,10 @@ defm : BWWriteResPair<WriteCLMul, [BWPo
def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
// AVX2.
-defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
-defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
-defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles.
-defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles.
+defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles.
+defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles.
+defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector shuffles.
+defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector variable shuffles.
// Old microcoded instructions that nobody use.
def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
@@ -1242,23 +1242,6 @@ def: InstRW<[BWWriteResGroup101], (instr
"VCVTPS2DQYrm",
"VCVTTPS2DQYrm")>;
-def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
- let Latency = 9;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
- "VPERM2I128rm",
- "VPERMDYrm",
- "VPERMPDYmi",
- "VPERMPSYrm",
- "VPERMQYmi",
- "VPMOVZXBDYrm",
- "VPMOVZXBQYrm",
- "VPMOVZXBWYrm",
- "VPMOVZXDQYrm",
- "VPMOVZXWQYrm")>;
-
def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
let Latency = 9;
let NumMicroOps = 3;
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