[PATCH] D46158: [DAGCombiner] Set the right SDLoc on a newly-created sextload

[Vedant Kumar via Phabricator via llvm-commits]

vsk updated this revision to Diff 145976.
vsk edited the summary of this revision.
vsk added a comment.

Ping. I think there was still a question about register allocation changes which result from specifying the right IROrder. Is this something to be addressed in the scheduler, or should I be retaining the old IROrder here?


https://reviews.llvm.org/D46158

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/arm64-ldp-cluster.ll
  test/CodeGen/X86/avx512-insert-extract.ll
  test/CodeGen/X86/fold-sext-trunc.ll
  test/CodeGen/X86/known-signbits-vector.ll
  test/CodeGen/X86/pr32284.ll
  test/CodeGen/X86/vector-shuffle-variable-128.ll
  test/CodeGen/X86/vector-shuffle-variable-256.ll
  test/CodeGen/X86/widen_arith-4.ll
  test/CodeGen/X86/widen_arith-5.ll

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