[PATCH] D46655: [AArch64] Improve single vector lane stores

[Evandro Menezes via Phabricator via llvm-commits]

evandro created this revision.
evandro added reviewers: ab, SjoerdMeijer.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, rengolin.
Herald added a reviewer: javed.absar.

When storing the 0th lane of a vector, use a simpler and usually more efficient scalar store instead.


Repository:
  rL LLVM

https://reviews.llvm.org/D46655

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
  llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
  llvm/test/CodeGen/AArch64/arm64-st1.ll
  llvm/test/CodeGen/AArch64/fp16-vector-load-store.ll

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