[llvm] r331906 - AMDGPU: Stop special casing constant indexes of extract_vector_elt

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed May  9 11:29:26 2018
New Revision: 331906

URL: http://llvm.org/viewvc/llvm-project?rev=331906&view=rev
Log:
AMDGPU: Stop special casing constant indexes of extract_vector_elt

The same result folds out of the dynamic expansion logic if the
index is constant.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=331906&r1=331905&r2=331906&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Wed May  9 11:29:26 2018
@@ -4201,21 +4201,6 @@ SDValue SITargetLowering::lowerEXTRACT_V
   if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
     return Combined;
 
-  if (const ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
-    SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
-
-    if (CIdx->getZExtValue() == 1) {
-      Result = DAG.getNode(ISD::SRL, SL, MVT::i32, Result,
-                           DAG.getConstant(16, SL, MVT::i32));
-    } else {
-      assert(CIdx->getZExtValue() == 0);
-    }
-
-    if (ResultVT.bitsLT(MVT::i32))
-      Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Result);
-    return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
-  }
-
   SDValue Four = DAG.getConstant(4, SL, MVT::i32);
 
   // Convert vector index to bit-index (* 16)