[PATCH] D46647: [InstCombine] Teach SimplifyDemandedBits that udiv doesn't demand low dividend bits that are zero in the divisor

[Benjamin Kramer via Phabricator via llvm-commits]

bkramer added inline comments.


================
Comment at: lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:556
+
+      APInt DemandedMaskIn =
+          APInt::getHighBitsSet(BitWidth, BitWidth - SA->countTrailingZeros());
----------------
sanjoy wrote:
> Can we also propagate the demanded bits of the division result (in some form) into `DemandedMaskIn`?
Maybe. This is hard for non-power of 2 divisors though and probably not worth the effort :|


Repository:
  rL LLVM

https://reviews.llvm.org/D46647