[PATCH] D46649: [AggressiveInstCombine] convert a chain of 'and-shift' bits into masked compare

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: kparzysz, lebedev.ri, yamauchi.
Herald added a subscriber: mcrosier.

This is a follow-up to https://reviews.llvm.org/D45986. As suggested there, we should match the "all-bits-set" pattern in addition to "any-bits-set".

This was a little more complicated than I thought it would be initially because the "and 1" instruction can be anywhere in the chain. Hopefully, the code comments make that logic understandable, but if you see a way to simplify or improve that, it's most appreciated.

This transforms patterns that emerge from bitfield tests as seen in PR37098:
https://bugs.llvm.org/show_bug.cgi?id=37098

I think it would also help reduce the large test from https://reviews.llvm.org/D46336 / https://reviews.llvm.org/D46595, but we need something to reassociate that case to the forms we're expecting here first. Alternatively, we could extend the matching here to account for that pattern (but I have not investigated what that would take).


https://reviews.llvm.org/D46649

Files:
  lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
  test/Transforms/AggressiveInstCombine/masked-cmp.ll
  test/Transforms/PhaseOrdering/bitfield-bittests.ll

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