[PATCH] D46008: [X86][AArch64][NFC] Add tests for vector masked merge unfolding

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll:13
+; CHECK-SSE-NEXT:    movaps (%rcx), %xmm0
+; CHECK-SSE-NEXT:    movaps {{.*#+}} xmm1 = [nan,nan,nan,nan]
+; CHECK-SSE-NEXT:    xorps %xmm0, %xmm1
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Irrelevant to this patch but interesting that SSE1 can't do the xops+cmpps approach to generate all-ones (like we do on AVX1 for YMM)


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Comment at: test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=-sse,-sse2 < %s | FileCheck %s --check-prefix=CHECK-BASELINE
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,-sse2 < %s | FileCheck %s --check-prefix=CHECK-SSE
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lebedev.ri wrote:
> spatel wrote:
> > Why is this config interesting? IMO, it just distracts from the cases that we do care about, but I may not be seeing it.
> I think we do want to check that we don't do anything stupid in `andn`-less case,
> much like without `BMI` in scalar case. 
I agree, the non-SSE tests aren't very useful (and I'm a little dubious about SSE1 tbh).

What MIGHT be useful is a XOP pass:

; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,-sse2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE,CHECK-SSE1
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,+sse2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE,CHECK-SSE2
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+xop < %s | FileCheck %s --check-prefix=CHECK,CHECK-XOP

As XOP is the only X86 ISA with a bsl style vector instruction (PCMOV) - maybe add this to both x86 test files?


Repository:
  rL LLVM

https://reviews.llvm.org/D46008