[llvm] r331885 - [LV] Change MaxVectorSize bound to 256 in assertion, NFC otherwise

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed May  9 08:18:12 2018
New Revision: 331885

URL: http://llvm.org/viewvc/llvm-project?rev=331885&view=rev
Log:
[LV] Change MaxVectorSize bound to 256 in assertion, NFC otherwise

It's possible to have a vector of 256 bytes in HVX code on Hexagon
(vector pair in 128-byte mode).

Modified:
    llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp

Modified: llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp?rev=331885&r1=331884&r2=331885&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp (original)
+++ llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp Wed May  9 08:18:12 2018
@@ -4937,8 +4937,8 @@ LoopVectorizationCostModel::computeFeasi
   DEBUG(dbgs() << "LV: The Widest register safe to use is: " << WidestRegister
                << " bits.\n");
 
-  assert(MaxVectorSize <= 64 && "Did not expect to pack so many elements"
-                                " into one vector!");
+  assert(MaxVectorSize <= 256 && "Did not expect to pack so many elements"
+                                 " into one vector!");
   if (MaxVectorSize == 0) {
     DEBUG(dbgs() << "LV: The target has no vector registers.\n");
     MaxVectorSize = 1;