[PATCH] D46620: Fix side effect in debug code

[Eitan Adler via Phabricator via llvm-commits]

eax created this revision.
Herald added a subscriber: llvm-commits.

Use "+ 1" instead of "++" for the assertion


Repository:
  rL LLVM

https://reviews.llvm.org/D46620

Files:
  utils/TableGen/RegisterBankEmitter.cpp


Index: utils/TableGen/RegisterBankEmitter.cpp
===================================================================
--- utils/TableGen/RegisterBankEmitter.cpp
+++ utils/TableGen/RegisterBankEmitter.cpp
@@ -269,7 +269,7 @@
      << "#ifndef NDEBUG\n"
      << "  unsigned Index = 0;\n"
      << "  for (const auto &RB : RegBanks)\n"
-     << "    assert(Index++ == RB->getID() && \"Index != ID\");\n"
+     << "    assert(Index + 1 == RB->getID() && \"Index != ID\");\n"
      << "#endif // NDEBUG\n"
      << "}\n"
      << "} // end namespace llvm\n";


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D46620.145840.patch
Type: text/x-patch
Size: 551 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180509/7ed57ed9/attachment.bin>