[llvm] r331792 - DAG: Use correct shift width type

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Tue May  8 11:43:05 2018
New Revision: 331792

URL: http://llvm.org/viewvc/llvm-project?rev=331792&view=rev
Log:
DAG: Use correct shift width type

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=331792&r1=331791&r2=331792&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Tue May  8 11:43:05 2018
@@ -1076,7 +1076,7 @@ SDValue DAGTypeLegalizer::JoinIntegers(S
   Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi);
   Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi,
                    DAG.getConstant(LVT.getSizeInBits(), dlHi,
-                                   TLI.getPointerTy(DAG.getDataLayout())));
+                                   TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
   return DAG.getNode(ISD::OR, dlHi, NVT, Lo, Hi);
 }