[llvm] r331755 - [AArch64] Disallow vector operand if FPR128 Q register is required.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Tue May 8 10:03:37 PDT 2018
> On 8 May 2018, at 11:01, Sander de Smalen via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>
> Author: s.desmalen
> Date: Tue May 8 03:01:04 2018
> New Revision: 331755
>
> URL: http://llvm.org/viewvc/llvm-project?rev=331755&view=rev
> Log:
> [AArch64] Disallow vector operand if FPR128 Q register is required.
>
> Patch https://reviews.llvm.org/D41445 changed the behaviour of 'isReg()'
> to also return 'true' if the parsed register operand is a vector
> register. Code in the AsmMatcher checks if a register is a subclass of the
> expected register class. However, even though both parsed registers map
> to the same physical register, the 'v' register is of kind 'NeonVector',
> where 'q' is of type Scalar, where isSubclass() does not distinguish
> between the two cases.
>
> The solution is to use an AsmOperand instead of the register directly,
> and use the PredicateMethod to distinguish the two operands.
>
> This fixes for example:
> ldr v0, [x0] // 'v0' is an invalid operand for this instruction
> ldr q0, [x0] // valid
>
> Reviewers: aemerson, Gerolf, SjoerdMeijer, javed.absar
>
> Reviewed By: aemerson
>
> Differential Revision: https://reviews.llvm.org/D46310
>
>
> Modified:
> llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
> llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
> llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=331755&r1=331754&r2=331755&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Tue May 8 03:01:04 2018
> @@ -2684,7 +2684,7 @@ class BaseLoadStoreUI<bits<2> sz, bit V,
> let DecoderMethod = "DecodeUnsignedLdStInstruction";
> }
>
> -multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> Operand indextype, string asm, list<dag> pattern> {
> let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
> def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
> @@ -2696,7 +2696,7 @@ multiclass LoadUI<bits<2> sz, bit V, bit
> (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
> }
>
> -multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> Operand indextype, string asm, list<dag> pattern> {
> let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
> def ui : BaseLoadStoreUI<sz, V, opc, (outs),
> @@ -2756,7 +2756,7 @@ def am_ldrlit : Operand<iPTR> {
> }
>
> let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
> -class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
> +class LoadLiteral<bits<2> opc, bit V, RegisterOperand regtype, string asm>
> : I<(outs regtype:$Rt), (ins am_ldrlit:$label),
> asm, "\t$Rt, $label", "", []>,
> Sched<[WriteLD]> {
> @@ -2867,7 +2867,7 @@ def ro64 : ROAddrMode<ro_Windexed64, ro_
> def ro128 : ROAddrMode<ro_Windexed128, ro_Xindexed128, ro_Wextend128,
> ro_Xextend128>;
>
> -class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, dag ins, dag outs, list<dag> pat>
> : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
> bits<5> Rt;
> @@ -2889,11 +2889,11 @@ class LoadStore8RO<bits<2> sz, bit V, bi
> let Inst{4-0} = Rt;
> }
>
> -class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
> +class ROInstAlias<string asm, RegisterOperand regtype, Instruction INST>
> : InstAlias<asm # "\t$Rt, [$Rn, $Rm]",
> (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
>
> -multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, ValueType Ty, SDPatternOperator loadop> {
> let AddedComplexity = 10 in
> def roW : LoadStore8RO<sz, V, opc, regtype, asm,
> @@ -2920,7 +2920,7 @@ multiclass Load8RO<bits<2> sz, bit V, bi
> def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
> }
>
> -multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, ValueType Ty, SDPatternOperator storeop> {
> let AddedComplexity = 10 in
> def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
> @@ -2945,7 +2945,7 @@ multiclass Store8RO<bits<2> sz, bit V, b
> def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
> }
>
> -class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, dag ins, dag outs, list<dag> pat>
> : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
> bits<5> Rt;
> @@ -2967,7 +2967,7 @@ class LoadStore16RO<bits<2> sz, bit V, b
> let Inst{4-0} = Rt;
> }
>
> -multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, ValueType Ty, SDPatternOperator loadop> {
> let AddedComplexity = 10 in
> def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
> @@ -2992,7 +2992,7 @@ multiclass Load16RO<bits<2> sz, bit V, b
> def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
> }
>
> -multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, ValueType Ty, SDPatternOperator storeop> {
> let AddedComplexity = 10 in
> def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
> @@ -3017,7 +3017,7 @@ multiclass Store16RO<bits<2> sz, bit V,
> def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
> }
>
> -class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, dag ins, dag outs, list<dag> pat>
> : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
> bits<5> Rt;
> @@ -3039,7 +3039,7 @@ class LoadStore32RO<bits<2> sz, bit V, b
> let Inst{4-0} = Rt;
> }
>
> -multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, ValueType Ty, SDPatternOperator loadop> {
> let AddedComplexity = 10 in
> def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
> @@ -3064,7 +3064,7 @@ multiclass Load32RO<bits<2> sz, bit V, b
> def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
> }
>
> -multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, ValueType Ty, SDPatternOperator storeop> {
> let AddedComplexity = 10 in
> def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
> @@ -3089,7 +3089,7 @@ multiclass Store32RO<bits<2> sz, bit V,
> def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
> }
>
> -class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, dag ins, dag outs, list<dag> pat>
> : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
> bits<5> Rt;
> @@ -3111,7 +3111,7 @@ class LoadStore64RO<bits<2> sz, bit V, b
> let Inst{4-0} = Rt;
> }
>
> -multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, ValueType Ty, SDPatternOperator loadop> {
> let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
> def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
> @@ -3136,7 +3136,7 @@ multiclass Load64RO<bits<2> sz, bit V, b
> def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
> }
>
> -multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, ValueType Ty, SDPatternOperator storeop> {
> let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
> def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
> @@ -3161,7 +3161,7 @@ multiclass Store64RO<bits<2> sz, bit V,
> def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
> }
>
> -class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, dag ins, dag outs, list<dag> pat>
> : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
> bits<5> Rt;
> @@ -3183,7 +3183,7 @@ class LoadStore128RO<bits<2> sz, bit V,
> let Inst{4-0} = Rt;
> }
>
> -multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, ValueType Ty, SDPatternOperator loadop> {
> let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
> def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
> @@ -3208,7 +3208,7 @@ multiclass Load128RO<bits<2> sz, bit V,
> def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
> }
>
> -multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, ValueType Ty, SDPatternOperator storeop> {
> let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
> def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
> @@ -3322,7 +3322,7 @@ class BaseLoadStoreUnscale<bits<2> sz, b
> let DecoderMethod = "DecodeSignedLdStInstruction";
> }
>
> -multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, list<dag> pattern> {
> let AddedComplexity = 1 in // try this before LoadUI
> def i : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
> @@ -3333,7 +3333,7 @@ multiclass LoadUnscaled<bits<2> sz, bit
> (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
> }
>
> -multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, list<dag> pattern> {
> let AddedComplexity = 1 in // try this before StoreUI
> def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
> @@ -3430,7 +3430,7 @@ class BaseLoadStorePreIdx<bits<2> sz, bi
>
> let hasSideEffects = 0 in {
> let mayStore = 0, mayLoad = 1 in
> -class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm>
> : BaseLoadStorePreIdx<sz, V, opc,
> (outs GPR64sp:$wback, regtype:$Rt),
> @@ -3439,7 +3439,7 @@ class LoadPreIdx<bits<2> sz, bit V, bits
> Sched<[WriteLD, WriteAdr]>;
>
> let mayStore = 1, mayLoad = 0 in
> -class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, SDPatternOperator storeop, ValueType Ty>
> : BaseLoadStorePreIdx<sz, V, opc,
> (outs GPR64sp:$wback),
> @@ -3476,7 +3476,7 @@ class BaseLoadStorePostIdx<bits<2> sz, b
>
> let hasSideEffects = 0 in {
> let mayStore = 0, mayLoad = 1 in
> -class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm>
> : BaseLoadStorePostIdx<sz, V, opc,
> (outs GPR64sp:$wback, regtype:$Rt),
> @@ -3485,7 +3485,7 @@ class LoadPostIdx<bits<2> sz, bit V, bit
> Sched<[WriteLD, WriteAdr]>;
>
> let mayStore = 1, mayLoad = 0 in
> -class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
> +class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
> string asm, SDPatternOperator storeop, ValueType Ty>
> : BaseLoadStorePostIdx<sz, V, opc,
> (outs GPR64sp:$wback),
> @@ -3523,7 +3523,7 @@ class BaseLoadStorePairOffset<bits<2> op
> let DecoderMethod = "DecodePairLdStInstruction";
> }
>
> -multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
> +multiclass LoadPairOffset<bits<2> opc, bit V, RegisterOperand regtype,
> Operand indextype, string asm> {
> let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
> def i : BaseLoadStorePairOffset<opc, V, 1,
> @@ -3537,7 +3537,7 @@ multiclass LoadPairOffset<bits<2> opc, b
> }
>
>
> -multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
> +multiclass StorePairOffset<bits<2> opc, bit V, RegisterOperand regtype,
> Operand indextype, string asm> {
> let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
> def i : BaseLoadStorePairOffset<opc, V, 0, (outs),
> @@ -3574,7 +3574,7 @@ class BaseLoadStorePairPreIdx<bits<2> op
>
> let hasSideEffects = 0 in {
> let mayStore = 0, mayLoad = 1 in
> -class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
> +class LoadPairPreIdx<bits<2> opc, bit V, RegisterOperand regtype,
> Operand indextype, string asm>
> : BaseLoadStorePairPreIdx<opc, V, 1,
> (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
> @@ -3582,7 +3582,7 @@ class LoadPairPreIdx<bits<2> opc, bit V,
> Sched<[WriteLD, WriteLDHi, WriteAdr]>;
>
> let mayStore = 1, mayLoad = 0 in
> -class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
> +class StorePairPreIdx<bits<2> opc, bit V, RegisterOperand regtype,
> Operand indextype, string asm>
> : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback),
> (ins regtype:$Rt, regtype:$Rt2,
> @@ -3615,7 +3615,7 @@ class BaseLoadStorePairPostIdx<bits<2> o
>
> let hasSideEffects = 0 in {
> let mayStore = 0, mayLoad = 1 in
> -class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
> +class LoadPairPostIdx<bits<2> opc, bit V, RegisterOperand regtype,
> Operand idxtype, string asm>
> : BaseLoadStorePairPostIdx<opc, V, 1,
> (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
> @@ -3623,7 +3623,7 @@ class LoadPairPostIdx<bits<2> opc, bit V
> Sched<[WriteLD, WriteLDHi, WriteAdr]>;
>
> let mayStore = 1, mayLoad = 0 in
> -class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
> +class StorePairPostIdx<bits<2> opc, bit V, RegisterOperand regtype,
> Operand idxtype, string asm>
> : BaseLoadStorePairPostIdx<opc, V, 0, (outs GPR64sp:$wback),
> (ins regtype:$Rt, regtype:$Rt2,
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=331755&r1=331754&r2=331755&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Tue May 8 03:01:04 2018
> @@ -1439,39 +1439,39 @@ def : InstAlias<"dcps3", (DCPS3 0)>;
> //===----------------------------------------------------------------------===//
>
> // Pair (indexed, offset)
> -defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
> -defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
> -defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
> -defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
> -defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
> +defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">;
> +defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">;
> +defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">;
> +defm LDPD : LoadPairOffset<0b01, 1, FPR64Op, simm7s8, "ldp">;
> +defm LDPQ : LoadPairOffset<0b10, 1, FPR128Op, simm7s16, "ldp">;
>
> -defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
> +defm LDPSW : LoadPairOffset<0b01, 0, GPR64z, simm7s4, "ldpsw">;
>
> // Pair (pre-indexed)
> -def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
> -def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
> -def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
> -def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
> -def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
> +def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32z, simm7s4, "ldp">;
> +def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64z, simm7s8, "ldp">;
> +def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32Op, simm7s4, "ldp">;
> +def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64Op, simm7s8, "ldp">;
> +def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128Op, simm7s16, "ldp">;
>
> -def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
> +def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">;
>
> // Pair (post-indexed)
> -def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
> -def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
> -def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
> -def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
> -def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
> +def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32z, simm7s4, "ldp">;
> +def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64z, simm7s8, "ldp">;
> +def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32Op, simm7s4, "ldp">;
> +def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64Op, simm7s8, "ldp">;
> +def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128Op, simm7s16, "ldp">;
>
> -def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
> +def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">;
>
>
> // Pair (no allocate)
> -defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
> -defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
> -defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
> -defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
> -defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
> +defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32z, simm7s4, "ldnp">;
> +defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64z, simm7s8, "ldnp">;
> +defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32Op, simm7s4, "ldnp">;
> +defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64Op, simm7s8, "ldnp">;
> +defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128Op, simm7s16, "ldnp">;
Hi Sander,
One thing I noticed while testing this manually was that if you specify -mattr=+sve with llvm-mc, the error message you get is "error: invalid predicate register” rather than "error: invalid operand for instruction” when using just neon. This isn’t a big issue as SVE isn’t enabled by default but is a diagnostics issue for SVE users.
Cheers,
Amara
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