[llvm] r331756 - [mips] Mark various memory instructions as being in microMIPS (NFC)
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue May 8 03:16:21 PDT 2018
Author: sdardis
Date: Tue May 8 03:16:21 2018
New Revision: 331756
URL: http://llvm.org/viewvc/llvm-project?rev=331756&view=rev
Log:
[mips] Mark various memory instructions as being in microMIPS (NFC)
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46388
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/test/MC/Mips/micromips-loadstore-instructions.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=331756&r1=331755&r2=331756&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Tue May 8 03:16:21 2018
@@ -852,10 +852,9 @@ let DecoderNamespace = "MicroMips" in {
POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>,
ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
}
-}
-let DecoderNamespace = "MicroMips" in {
- let Predicates = [InMicroMips] in
- def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
+
+ def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>,
+ ISA_MICROMIPS;
/// Load and Store Instructions - unaligned
def LWL_MM : MMRel, LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12,
@@ -873,12 +872,12 @@ let DecoderNamespace = "MicroMips" in {
}
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
/// Load and Store Instructions - multiple
- def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>;
- def LWM32_MM : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>;
+ def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>, ISA_MICROMIPS;
+ def LWM32_MM : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>, ISA_MICROMIPS;
/// Load and Store Pair Instructions
- def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
- def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
+ def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>, ISA_MICROMIPS;
+ def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>, ISA_MICROMIPS;
/// Load and Store multiple pseudo Instructions
class LoadWordMultMM<string instr_asm > :
@@ -890,8 +889,8 @@ let DecoderNamespace = "MicroMips", Pred
!strconcat(instr_asm, "\t$rt, $addr")> ;
- def SWM_MM : StoreWordMultMM<"swm">;
- def LWM_MM : LoadWordMultMM<"lwm">;
+ def SWM_MM : StoreWordMultMM<"swm">, ISA_MICROMIPS;
+ def LWM_MM : LoadWordMultMM<"lwm">, ISA_MICROMIPS;
/// Move Conditional
def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
Modified: llvm/trunk/test/MC/Mips/micromips-loadstore-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-loadstore-instructions.s?rev=331756&r1=331755&r2=331756&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-loadstore-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-loadstore-instructions.s Tue May 8 03:16:21 2018
@@ -1,6 +1,6 @@
-# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
+# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips -show-inst \
# RUN: | FileCheck -check-prefix=CHECK-EL %s
-# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
+# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips -show-inst \
# RUN: | FileCheck -check-prefix=CHECK-EB %s
# Check that the assembler can handle the documented syntax
# for load and store instructions.
@@ -24,26 +24,47 @@
# CHECK-EL: sc $2, 8($4) # encoding: [0x44,0x60,0x08,0xb0]
# CHECK-EL: lwu $2, 8($4) # encoding: [0x44,0x60,0x08,0xe0]
# CHECK-EL: lwxs $2, $3($4) # encoding: [0x64,0x00,0x18,0x11]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWXS_MM
# CHECK-EL: lwm32 $16, $17, 8($4) # encoding: [0x44,0x20,0x08,0x50]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EL: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0x50]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EL: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x24,0x21,0x08,0x50]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EL: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x84,0x22,0x08,0x50]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EL: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x24,0x23,0x08,0x50]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EL: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x24,0x23,0x08,0x50]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EL: swm32 $16, $17, 8($4) # encoding: [0x44,0x20,0x08,0xd0]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWM32_MM
# CHECK-EL: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0xd0]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWM32_MM
# CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM16_MM
# CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWM16_MM
# CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM16_MM
# CHECK-EL: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x5d,0x22,0x40,0x50]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EL: lwm32 $16, $17, $ra, 8($4) # encoding: [0x44,0x22,0x08,0x50]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EL: lwm32 $16, $17, 8($sp) # encoding: [0x5d,0x20,0x08,0x50]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWM16_MM
# CHECK-EL: swm32 $16, $17, $ra, 64($sp) # encoding: [0x5d,0x22,0x40,0xd0]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWM32_MM
# CHECK-EL: swm32 $16, $17, $ra, 8($4) # encoding: [0x44,0x22,0x08,0xd0]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWM32_MM
# CHECK-EL: swm32 $16, $17, 8($sp) # encoding: [0x5d,0x20,0x08,0xd0]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWM32_MM
# CHECK-EL: swp $16, 8($4) # encoding: [0x04,0x22,0x08,0x90]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWP_MM
# CHECK-EL: lwp $16, 8($4) # encoding: [0x04,0x22,0x08,0x10]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWP_MM
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@@ -62,26 +83,47 @@
# CHECK-EB: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
# CHECK-EB: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08]
# CHECK-EB: lwxs $2, $3($4) # encoding: [0x00,0x64,0x11,0x18]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWXS_MM
# CHECK-EB: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EB: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EB: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EB: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EB: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EB: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EB: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWM32_MM
# CHECK-EB: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWM32_MM
# CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM16_MM
# CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWM16_MM
# CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM16_MM
# CHECK-EB: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EB: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EB: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
# CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWM16_MM
# CHECK-EB: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWM32_MM
# CHECK-EB: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWM32_MM
# CHECK-EB: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWM32_MM
# CHECK-EB: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWP_MM
# CHECK-EB: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWP_MM
lb $5, 8($4)
lbu $6, 8($4)
lh $2, 8($4)
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