[llvm] r331742 - [x86] Introduce the enclv instruction
Gabor Buella via llvm-commits
llvm-commits at lists.llvm.org
Tue May 8 00:11:06 PDT 2018
Author: gbuella
Date: Tue May 8 00:11:05 2018
New Revision: 331742
URL: http://llvm.org/viewvc/llvm-project?rev=331742&view=rev
Log:
[x86] Introduce the enclv instruction
Summary:
and use the -msgx flag as a requirement
for the SGX instructions.
Reviewers: craig.topper, zvi
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D46436
Removed:
llvm/trunk/test/MC/X86/SGX-32.s
llvm/trunk/test/MC/X86/SGX-64.s
llvm/trunk/test/MC/X86/sgx-encoding.s
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrSGX.td
llvm/trunk/lib/Target/X86/X86Subtarget.h
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
llvm/trunk/test/MC/X86/x86-32-coverage.s
llvm/trunk/test/MC/X86/x86-64.s
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=331742&r1=331741&r2=331742&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue May 8 00:11:05 2018
@@ -881,6 +881,7 @@ def HasIFMA : Predicate<"Subtarget-
def HasRTM : Predicate<"Subtarget->hasRTM()">;
def HasADX : Predicate<"Subtarget->hasADX()">;
def HasSHA : Predicate<"Subtarget->hasSHA()">;
+def HasSGX : Predicate<"Subtarget->hasSGX()">;
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
Modified: llvm/trunk/lib/Target/X86/X86InstrSGX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSGX.td?rev=331742&r1=331741&r2=331742&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSGX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSGX.td Tue May 8 00:11:05 2018
@@ -15,7 +15,7 @@
//===----------------------------------------------------------------------===//
// SGX instructions
-let SchedRW = [WriteSystem] in {
+let SchedRW = [WriteSystem], Predicates = [HasSGX] in {
// ENCLS - Execute an Enclave System Function of Specified Leaf Number
def ENCLS : I<0x01, MRM_CF, (outs), (ins),
"encls", []>, TB;
@@ -23,4 +23,8 @@ def ENCLS : I<0x01, MRM_CF, (outs), (ins
// ENCLU - Execute an Enclave User Function of Specified Leaf Number
def ENCLU : I<0x01, MRM_D7, (outs), (ins),
"enclu", []>, TB;
+
+// ENCLV - Execute an Enclave VMM Function of Specified Leaf Number
+def ENCLV : I<0x01, MRM_C0, (outs), (ins),
+ "enclv", []>, TB;
} // SchedRW
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=331742&r1=331741&r2=331742&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Tue May 8 00:11:05 2018
@@ -644,6 +644,7 @@ public:
bool hasRDPID() const { return HasRDPID; }
bool hasWAITPKG() const { return HasWAITPKG; }
bool hasPCONFIG() const { return HasPCONFIG; }
+ bool hasSGX() const { return HasSGX; }
bool useRetpoline() const { return UseRetpoline; }
bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=331742&r1=331741&r2=331742&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Tue May 8 00:11:05 2018
@@ -874,3 +874,12 @@
#CHECK: pconfig
0x0f 0x01 0xc5
+
+#CHECK: encls
+0x0f 0x01 0xcf
+
+#CHECK: enclu
+0x0f 0x01 0xd7
+
+#CHECK: enclv
+0x0f 0x01 0xc0
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-64.txt?rev=331742&r1=331741&r2=331742&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-64.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-64.txt Tue May 8 00:11:05 2018
@@ -567,3 +567,12 @@
#CHECK: pconfig
0x0f 0x01 0xc5
+
+#CHECK: encls
+0x0f 0x01 0xcf
+
+#CHECK: enclu
+0x0f 0x01 0xd7
+
+#CHECK: enclv
+0x0f 0x01 0xc0
Removed: llvm/trunk/test/MC/X86/SGX-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/SGX-32.s?rev=331741&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/SGX-32.s (original)
+++ llvm/trunk/test/MC/X86/SGX-32.s (removed)
@@ -1,10 +0,0 @@
-// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
-
-// CHECK: encls
-// CHECK: encoding: [0x0f,0x01,0xcf]
-encls
-
-// CHECK: enclu
-// CHECK: encoding: [0x0f,0x01,0xd7]
-enclu
-
Removed: llvm/trunk/test/MC/X86/SGX-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/SGX-64.s?rev=331741&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/SGX-64.s (original)
+++ llvm/trunk/test/MC/X86/SGX-64.s (removed)
@@ -1,10 +0,0 @@
-// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
-
-// CHECK: encls
-// CHECK: encoding: [0x0f,0x01,0xcf]
-encls
-
-// CHECK: enclu
-// CHECK: encoding: [0x0f,0x01,0xd7]
-enclu
-
Removed: llvm/trunk/test/MC/X86/sgx-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/sgx-encoding.s?rev=331741&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/sgx-encoding.s (original)
+++ llvm/trunk/test/MC/X86/sgx-encoding.s (removed)
@@ -1,9 +0,0 @@
-// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
-
-// CHECK: encls
-// CHECK: encoding: [0x0f,0x01,0xcf]
- encls
-
-// CHECK: enclu
-// CHECK: encoding: [0x0f,0x01,0xd7]
- enclu
Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=331742&r1=331741&r2=331742&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-coverage.s (original)
+++ llvm/trunk/test/MC/X86/x86-32-coverage.s Tue May 8 00:11:05 2018
@@ -10796,3 +10796,15 @@ btcl $4, (%eax)
// CHECK: pconfig
// CHECK: # encoding: [0x0f,0x01,0xc5]
pconfig
+
+// CHECK: encls
+// CHECK: encoding: [0x0f,0x01,0xcf]
+encls
+
+// CHECK: enclu
+// CHECK: encoding: [0x0f,0x01,0xd7]
+enclu
+
+// CHECK: enclv
+// CHECK: encoding: [0x0f,0x01,0xc0]
+enclv
Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=331742&r1=331741&r2=331742&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Tue May 8 00:11:05 2018
@@ -1623,6 +1623,18 @@ movdir64b (%rdx), %r15
// CHECK: # encoding: [0x0f,0x01,0xc5]
pconfig
+// CHECK: encls
+// CHECK: encoding: [0x0f,0x01,0xcf]
+encls
+
+// CHECK: enclu
+// CHECK: encoding: [0x0f,0x01,0xd7]
+enclu
+
+// CHECK: enclv
+// CHECK: encoding: [0x0f,0x01,0xc0]
+enclv
+
// __asm __volatile(
// "pushf \n\t"
// "popf \n\t"
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