[llvm] r331739 - [x86] Introduce the pconfig instruction
Gabor Buella via llvm-commits
llvm-commits at lists.llvm.org
Mon May 7 23:47:36 PDT 2018
Author: gbuella
Date: Mon May 7 23:47:36 2018
New Revision: 331739
URL: http://llvm.org/viewvc/llvm-project?rev=331739&view=rev
Log:
[x86] Introduce the pconfig instruction
Reviewers: craig.topper, zvi
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D46430
Modified:
llvm/trunk/lib/Support/Host.cpp
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrSystem.td
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.h
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
llvm/trunk/test/MC/X86/x86-32-coverage.s
llvm/trunk/test/MC/X86/x86-64.s
Modified: llvm/trunk/lib/Support/Host.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=331739&r1=331738&r2=331739&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Host.cpp (original)
+++ llvm/trunk/lib/Support/Host.cpp Mon May 7 23:47:36 2018
@@ -1266,6 +1266,18 @@ bool sys::getHostCPUFeatures(StringMap<b
Features["ibt"] = HasLeaf7 && ((EDX >> 20) & 1);
+ // There are two CPUID leafs which information associated with the pconfig
+ // instruction:
+ // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
+ // bit of EDX), while the EAX=0x1b leaf returns information on the
+ // availability of specific pconfig leafs.
+ // The target feature here only refers to the the first of these two.
+ // Users might need to check for the availability of specific pconfig
+ // leaves using cpuid, since that information is ignored while
+ // detecting features using the "-march=native" flag.
+ // For more info, see X86 ISA docs.
+ Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
+
bool HasLeafD = MaxLevel >= 0xd &&
!getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=331739&r1=331738&r2=331739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Mon May 7 23:47:36 2018
@@ -280,6 +280,8 @@ def FeaturePOPCNTFalseDeps : SubtargetFe
def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
"HasLZCNTFalseDeps", "true",
"LZCNT/TZCNT have a false dependency on dest register">;
+def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
+ "platform configuration instruction">;
// On recent X86 (port bound) processors, its preferable to combine to a single shuffle
// using a variable mask over multiple fixed shuffles.
def FeatureFastVariableShuffle
@@ -868,6 +870,7 @@ def : IcelakeClientProc<"icelake-client"
class IcelakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
ICLFeatures.Value, [
ProcIntelICX,
+ FeaturePCONFIG,
FeatureWBNOINVD,
FeatureHasFastGather
]>;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=331739&r1=331738&r2=331739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon May 7 23:47:36 2018
@@ -904,6 +904,7 @@ def HasWBNOINVD : Predicate<"Subtarget-
def HasRDPID : Predicate<"Subtarget->hasRDPID()">;
def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">;
def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
+def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">;
def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
def In64BitMode : Predicate<"Subtarget->is64Bit()">,
Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=331739&r1=331738&r2=331739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Mon May 7 23:47:36 2018
@@ -701,3 +701,20 @@ def PTWRITEr : I<0xAE, MRM4r, (outs), (i
def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
"ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;
} // SchedRW
+
+//===----------------------------------------------------------------------===//
+// Platform Configuration instruction
+
+// From ISA docs:
+// "This instruction is used to execute functions for configuring platform
+// features.
+// EAX: Leaf function to be invoked.
+// RBX/RCX/RDX: Leaf-specific purpose."
+// "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
+// AF, OF, and SF are cleared. In case of failure, the failure reason is
+// indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
+// Thus all these mentioned registers are considered clobbered.
+
+let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
+ def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB,
+ Requires<[HasPCONFIG]>;
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=331739&r1=331738&r2=331739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon May 7 23:47:36 2018
@@ -323,6 +323,7 @@ void X86Subtarget::initializeEnvironment
HasSHSTK = false;
HasIBT = false;
HasSGX = false;
+ HasPCONFIG = false;
HasCLFLUSHOPT = false;
HasCLWB = false;
HasWBNOINVD = false;
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=331739&r1=331738&r2=331739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon May 7 23:47:36 2018
@@ -379,6 +379,9 @@ protected:
/// Processor supports WaitPKG instructions
bool HasWAITPKG;
+ /// Processor supports PCONFIG instruction
+ bool HasPCONFIG;
+
/// Use a retpoline thunk rather than indirect calls to block speculative
/// execution.
bool UseRetpoline;
@@ -640,6 +643,7 @@ public:
bool hasWBNOINVD() const { return HasWBNOINVD; }
bool hasRDPID() const { return HasRDPID; }
bool hasWAITPKG() const { return HasWAITPKG; }
+ bool hasPCONFIG() const { return HasPCONFIG; }
bool useRetpoline() const { return UseRetpoline; }
bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=331739&r1=331738&r2=331739&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Mon May 7 23:47:36 2018
@@ -871,3 +871,6 @@
#CHECK: movdir64b (%si), %ax
0x67 0x66 0x0f 0x38 0xf8 0x04
+
+#CHECK: pconfig
+0x0f 0x01 0xc5
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-64.txt?rev=331739&r1=331738&r2=331739&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-64.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-64.txt Mon May 7 23:47:36 2018
@@ -564,3 +564,6 @@
#CHECK: movdir64b 485498096, %eax
0x67 0x66 0x0f 0x38 0xf8 0x04 0x25 0xf0 0x1c 0xf0 0x1c
+
+#CHECK: pconfig
+0x0f 0x01 0xc5
Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=331739&r1=331738&r2=331739&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-coverage.s (original)
+++ llvm/trunk/test/MC/X86/x86-32-coverage.s Mon May 7 23:47:36 2018
@@ -10792,3 +10792,7 @@ btcl $4, (%eax)
// CHECK: movdir64b (%si), %ax
// CHECK: # encoding: [0x67,0x66,0x0f,0x38,0xf8,0x04]
movdir64b (%si), %ax
+
+// CHECK: pconfig
+// CHECK: # encoding: [0x0f,0x01,0xc5]
+pconfig
Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=331739&r1=331738&r2=331739&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Mon May 7 23:47:36 2018
@@ -1619,6 +1619,10 @@ movdir64b 485498096, %eax
// CHECK: # encoding: [0x66,0x44,0x0f,0x38,0xf8,0x3a]
movdir64b (%rdx), %r15
+// CHECK: pconfig
+// CHECK: # encoding: [0x0f,0x01,0xc5]
+pconfig
+
// __asm __volatile(
// "pushf \n\t"
// "popf \n\t"
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