[llvm] r331684 - [DagCombiner] Not all 'andn''s work with immediates.
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Mon May 7 14:52:11 PDT 2018
Author: lebedevri
Date: Mon May 7 14:52:11 2018
New Revision: 331684
URL: http://llvm.org/viewvc/llvm-project?rev=331684&view=rev
Log:
[DagCombiner] Not all 'andn''s work with immediates.
Summary:
Split off from D46031.
In masked merge case, this degrades IPC by decreasing instruction count.
{F6108777}
The next patch should be able to recover and improve this.
This also affects the transform @spatel have added in D27489 / rL289738,
and the test coverage for X86 was missing.
But after i have added it, and looked at the changes in MCA, i'm somewhat confused.
{F6093591} {F6093592} {F6093593}
I'd say this regression is an improvement, since `IPC` increased in that case?
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: andreadb, llvm-commits, spatel
Differential Revision: https://reviews.llvm.org/D46493
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/test/CodeGen/X86/icmp-opt.ll
llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll
llvm/trunk/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=331684&r1=331683&r2=331684&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 7 14:52:11 2018
@@ -5428,6 +5428,10 @@ SDValue DAGCombiner::unfoldMaskedMerge(S
if (!TLI.hasAndNot(M))
return SDValue();
+ // If Y is a constant, check that 'andn' works with immediates.
+ if (!TLI.hasAndNot(Y))
+ return SDValue();
+
SDLoc DL(N);
SDValue LHS = DAG.getNode(ISD::AND, DL, VT, X, M);
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=331684&r1=331683&r2=331684&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon May 7 14:52:11 2018
@@ -4743,6 +4743,9 @@ bool X86TargetLowering::isMaskAndCmp0Fol
}
bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
+ // A mask and compare against constant is ok for an 'andn' too
+ // even though the BMI instruction doesn't have an immediate form.
+
if (!Subtarget.hasBMI())
return false;
@@ -4754,6 +4757,14 @@ bool X86TargetLowering::hasAndNotCompare
return true;
}
+bool X86TargetLowering::hasAndNot(SDValue Y) const {
+ // x86 can't form 'andn' with an immediate.
+ if (isa<ConstantSDNode>(Y))
+ return false;
+
+ return hasAndNotCompare(Y);
+}
+
MVT X86TargetLowering::hasFastEqualityCompare(unsigned NumBits) const {
MVT VT = MVT::getIntegerVT(NumBits);
if (isTypeLegal(VT))
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=331684&r1=331683&r2=331684&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon May 7 14:52:11 2018
@@ -834,6 +834,8 @@ namespace llvm {
bool hasAndNotCompare(SDValue Y) const override;
+ bool hasAndNot(SDValue Y) const override;
+
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
return VT.isScalarInteger();
}
Modified: llvm/trunk/test/CodeGen/X86/icmp-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/icmp-opt.ll?rev=331684&r1=331683&r2=331684&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/icmp-opt.ll (original)
+++ llvm/trunk/test/CodeGen/X86/icmp-opt.ll Mon May 7 14:52:11 2018
@@ -17,9 +17,9 @@ define i32 @t1(i64 %a) {
;
; CHECK-BMI-LABEL: t1:
; CHECK-BMI: # %bb.0:
-; CHECK-BMI-NEXT: shrq $63, %rdi
-; CHECK-BMI-NEXT: xorl $1, %edi
-; CHECK-BMI-NEXT: movl %edi, %eax
+; CHECK-BMI-NEXT: xorl %eax, %eax
+; CHECK-BMI-NEXT: testq %rdi, %rdi
+; CHECK-BMI-NEXT: setns %al
; CHECK-BMI-NEXT: retq
%cmp = icmp sgt i64 %a, -1
%conv = zext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll?rev=331684&r1=331683&r2=331684&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll (original)
+++ llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll Mon May 7 14:52:11 2018
@@ -101,10 +101,10 @@ define i32 @pos_sel_constants(i32 %a) {
;
; CHECK-BMI-LABEL: pos_sel_constants:
; CHECK-BMI: # %bb.0:
-; CHECK-BMI-NEXT: sarl $31, %edi
-; CHECK-BMI-NEXT: notl %edi
-; CHECK-BMI-NEXT: andl $5, %edi
-; CHECK-BMI-NEXT: movl %edi, %eax
+; CHECK-BMI-NEXT: xorl %eax, %eax
+; CHECK-BMI-NEXT: testl %edi, %edi
+; CHECK-BMI-NEXT: setns %al
+; CHECK-BMI-NEXT: leal (%rax,%rax,4), %eax
; CHECK-BMI-NEXT: retq
%tmp.1 = icmp sgt i32 %a, -1
%retval = select i1 %tmp.1, i32 5, i32 0
@@ -124,10 +124,10 @@ define i32 @pos_sel_special_constant(i32
;
; CHECK-BMI-LABEL: pos_sel_special_constant:
; CHECK-BMI: # %bb.0:
-; CHECK-BMI-NEXT: shrl $22, %edi
-; CHECK-BMI-NEXT: notl %edi
-; CHECK-BMI-NEXT: andl $512, %edi # imm = 0x200
-; CHECK-BMI-NEXT: movl %edi, %eax
+; CHECK-BMI-NEXT: xorl %eax, %eax
+; CHECK-BMI-NEXT: testl %edi, %edi
+; CHECK-BMI-NEXT: setns %al
+; CHECK-BMI-NEXT: shll $9, %eax
; CHECK-BMI-NEXT: retq
%tmp.1 = icmp sgt i32 %a, -1
%retval = select i1 %tmp.1, i32 512, i32 0
Modified: llvm/trunk/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll?rev=331684&r1=331683&r2=331684&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll (original)
+++ llvm/trunk/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll Mon May 7 14:52:11 2018
@@ -657,11 +657,10 @@ define i32 @in_constant_varx_42(i32 %x,
;
; CHECK-BMI-LABEL: in_constant_varx_42:
; CHECK-BMI: # %bb.0:
+; CHECK-BMI-NEXT: xorl $42, %edi
; CHECK-BMI-NEXT: andl %edx, %edi
-; CHECK-BMI-NEXT: notl %edx
-; CHECK-BMI-NEXT: andl $42, %edx
-; CHECK-BMI-NEXT: orl %edi, %edx
-; CHECK-BMI-NEXT: movl %edx, %eax
+; CHECK-BMI-NEXT: xorl $42, %edi
+; CHECK-BMI-NEXT: movl %edi, %eax
; CHECK-BMI-NEXT: retq
%n0 = xor i32 %x, 42 ; %x
%n1 = and i32 %n0, %mask
@@ -705,9 +704,9 @@ define i32 @in_constant_varx_42_invmask(
;
; CHECK-BMI-LABEL: in_constant_varx_42_invmask:
; CHECK-BMI: # %bb.0:
+; CHECK-BMI-NEXT: xorl $42, %edi
; CHECK-BMI-NEXT: andnl %edi, %edx, %eax
-; CHECK-BMI-NEXT: andl $42, %edx
-; CHECK-BMI-NEXT: orl %edx, %eax
+; CHECK-BMI-NEXT: xorl $42, %eax
; CHECK-BMI-NEXT: retq
%notmask = xor i32 %mask, -1
%n0 = xor i32 %x, 42 ; %x
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