[PATCH] D46532: AMDGPU: Stop special casing constant indexes of extract_vector_elt

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, kzhuravl, cfang.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng.

The same result folds out of the dynamic expansion logic if the
index is constant.


https://reviews.llvm.org/D46532

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp


Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4201,21 +4201,6 @@
   if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
     return Combined;
 
-  if (const ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
-    SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
-
-    if (CIdx->getZExtValue() == 1) {
-      Result = DAG.getNode(ISD::SRL, SL, MVT::i32, Result,
-                           DAG.getConstant(16, SL, MVT::i32));
-    } else {
-      assert(CIdx->getZExtValue() == 0);
-    }
-
-    if (ResultVT.bitsLT(MVT::i32))
-      Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Result);
-    return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
-  }
-
   SDValue Four = DAG.getConstant(4, SL, MVT::i32);
 
   // Convert vector index to bit-index (* 16)


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