[PATCH] D46470: [AMDGPU] Fixed a couple of SIFixWWMLiveness problems

[Connor Abbott via Phabricator via llvm-commits]

cwabbott added a comment.

In https://reviews.llvm.org/D46470#1088984, @tpr wrote:

> You made a comment in this code that "this is a workaround anyways until LLVM gains the notion of predicated uses and definitions of variables". How do you see that working? Are you aware of anyone else thinking along those lines in the LLVM community? Something to think about for the future.


I was thinking about some way to decorate instructions with abstract predicates with enough information to make them useful for register allocation. For example, you could compute the OR of two predicates, one predicate minus another, etc. We would compute these predicates per-block before lowering the control flow, and then make every instruction predicated and lower the control flow (preserving the predicates). Except that WWM instructions still wouldn't be predicated, of course. There's a lot of pre-existing literature on this sort of thing with classical (scalar) predicated architectures, for example "Strategies for Predicate-Aware Register Allocation" by Hoflehner is one overview. Actually implementing one of the schemes in that paper would require changes to core MC and would probably be quite invasive, though. There are some other potential users for it, like the new predicated AVX512 stuff, but I don't know if anyone else is thinking about it besides for some discussion with @nhaehnle.


Repository:
  rL LLVM

https://reviews.llvm.org/D46470