[llvm] r331604 - Add test cases for large integer legalization of add and sub. NFC

[Amaury Sechet via llvm-commits]

Author: deadalnix
Date: Sun May  6 09:00:23 2018
New Revision: 331604

URL: http://llvm.org/viewvc/llvm-project?rev=331604&view=rev
Log:
Add test cases for large integer legalization of add and sub. NFC

Modified:
    llvm/trunk/test/CodeGen/X86/addcarry.ll
    llvm/trunk/test/CodeGen/X86/subcarry.ll

Modified: llvm/trunk/test/CodeGen/X86/addcarry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/addcarry.ll?rev=331604&r1=331603&r2=331604&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/addcarry.ll (original)
+++ llvm/trunk/test/CodeGen/X86/addcarry.ll Sun May  6 09:00:23 2018
@@ -1,6 +1,37 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
 
+define i128 @add128(i128 %a, i128 %b) nounwind {
+; CHECK-LABEL: add128:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addq %rdx, %rdi
+; CHECK-NEXT:    adcq %rcx, %rsi
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    movq %rsi, %rdx
+; CHECK-NEXT:    retq
+entry:
+  %0 = add i128 %a, %b
+  ret i128 %0
+}
+
+define i256 @add256(i256 %a, i256 %b) nounwind {
+; CHECK-LABEL: add256:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addq %r9, %rsi
+; CHECK-NEXT:    adcq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT:    adcq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT:    adcq {{[0-9]+}}(%rsp), %r8
+; CHECK-NEXT:    movq %rdx, 8(%rdi)
+; CHECK-NEXT:    movq %rsi, (%rdi)
+; CHECK-NEXT:    movq %rcx, 16(%rdi)
+; CHECK-NEXT:    movq %r8, 24(%rdi)
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = add i256 %a, %b
+  ret i256 %0
+}
+
 define void @a(i64* nocapture %s, i64* nocapture %t, i64 %a, i64 %b, i64 %c) nounwind {
 ; CHECK-LABEL: a:
 ; CHECK:       # %bb.0: # %entry

Modified: llvm/trunk/test/CodeGen/X86/subcarry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/subcarry.ll?rev=331604&r1=331603&r2=331604&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/subcarry.ll (original)
+++ llvm/trunk/test/CodeGen/X86/subcarry.ll Sun May  6 09:00:23 2018
@@ -1,6 +1,37 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
 
+define i128 @sub128(i128 %a, i128 %b) nounwind {
+; CHECK-LABEL: sub128:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subq %rdx, %rdi
+; CHECK-NEXT:    sbbq %rcx, %rsi
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    movq %rsi, %rdx
+; CHECK-NEXT:    retq
+entry:
+  %0 = sub i128 %a, %b
+  ret i128 %0
+}
+
+define i256 @sub256(i256 %a, i256 %b) nounwind {
+; CHECK-LABEL: sub256:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subq %r9, %rsi
+; CHECK-NEXT:    sbbq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT:    sbbq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT:    sbbq {{[0-9]+}}(%rsp), %r8
+; CHECK-NEXT:    movq %rdx, 8(%rdi)
+; CHECK-NEXT:    movq %rsi, (%rdi)
+; CHECK-NEXT:    movq %rcx, 16(%rdi)
+; CHECK-NEXT:    movq %r8, 24(%rdi)
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = sub i256 %a, %b
+  ret i256 %0
+}
+
 %S = type { [4 x i64] }
 
 define %S @negate(%S* nocapture readonly %this) {