[llvm] r331551 - AMDGPU: Add D16 instructions preserve unused bits feature
Konstantin Zhuravlyov via llvm-commits
llvm-commits at lists.llvm.org
Fri May 4 13:06:58 PDT 2018
Author: kzhuravl
Date: Fri May 4 13:06:57 2018
New Revision: 331551
URL: http://llvm.org/viewvc/llvm-project?rev=331551&view=rev
Log:
AMDGPU: Add D16 instructions preserve unused bits feature
- Predicate D16 patterns on this new feature
- Added this new feature to gfx900/2/4
Differential Revision: https://reviews.llvm.org/D46366
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td
llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td
llvm/trunk/test/CodeGen/AMDGPU/load-hi16.ll
llvm/trunk/test/CodeGen/AMDGPU/store-hi16.ll
llvm/trunk/test/MC/AMDGPU/gfx9_asm_all.s
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPU.td?rev=331551&r1=331550&r2=331551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPU.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.td Fri May 4 13:06:57 2018
@@ -322,6 +322,13 @@ def FeatureDLInsts : SubtargetFeature<"d
"Has deep learning instructions"
>;
+def FeatureD16PreservesUnusedBits : SubtargetFeature<
+ "d16-preserves-unused-bits",
+ "D16PreservesUnusedBits",
+ "true",
+ "D16 memory instructions preserve unused bits rather than zeroing them out"
+>;
+
//===------------------------------------------------------------===//
// Subtarget Features (options and debugging)
//===------------------------------------------------------------===//
@@ -608,20 +615,23 @@ def FeatureISAVersion8_1_0 : SubtargetFe
def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
[FeatureGFX9,
FeatureMadMixInsts,
- FeatureLDSBankCount32
+ FeatureLDSBankCount32,
+ FeatureD16PreservesUnusedBits
]>;
def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
[FeatureGFX9,
FeatureMadMixInsts,
FeatureLDSBankCount32,
- FeatureXNACK
+ FeatureXNACK,
+ FeatureD16PreservesUnusedBits
]>;
def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
[FeatureGFX9,
FeatureLDSBankCount32,
- FeatureFmaMixInsts]>;
+ FeatureFmaMixInsts,
+ FeatureD16PreservesUnusedBits]>;
def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
[FeatureGFX9,
@@ -769,6 +779,8 @@ def HasUnpackedD16VMem : Predicate<"Subt
def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
AssemblerPredicate<"!FeatureUnpackedD16VMem">;
+def D16PreservesUnusedBits : Predicate<"Subtarget->d16PreservesUnusedBits()">,
+ AssemblerPredicate<"FeatureD16PreservesUnusedBits">;
def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=331551&r1=331550&r2=331551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Fri May 4 13:06:57 2018
@@ -162,6 +162,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const T
HasSDWAOutModsVOPC(false),
HasDPP(false),
HasDLInsts(false),
+ D16PreservesUnusedBits(false),
FlatAddressSpace(false),
FlatInstOffsets(false),
FlatGlobalInsts(false),
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=331551&r1=331550&r2=331551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h Fri May 4 13:06:57 2018
@@ -166,6 +166,7 @@ protected:
bool HasSDWAOutModsVOPC;
bool HasDPP;
bool HasDLInsts;
+ bool D16PreservesUnusedBits;
bool FlatAddressSpace;
bool FlatInstOffsets;
bool FlatGlobalInsts;
@@ -546,6 +547,10 @@ public:
return HasDLInsts;
}
+ bool d16PreservesUnusedBits() const {
+ return D16PreservesUnusedBits;
+ }
+
/// Returns the offset in bytes from the start of the input buffer
/// of the first explicit kernel argument.
unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const {
Modified: llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td?rev=331551&r1=331550&r2=331551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td Fri May 4 13:06:57 2018
@@ -1374,7 +1374,7 @@ defm : MUBUFScratchLoadPat <BUFFER_LOAD_
defm : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, BUFFER_LOAD_DWORDX2_OFFSET, v2i32, load_private>;
defm : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, BUFFER_LOAD_DWORDX4_OFFSET, v4i32, load_private>;
-let OtherPredicates = [HasD16LoadStore] in {
+let OtherPredicates = [D16PreservesUnusedBits] in {
defm : MUBUFScratchLoadPat_Hi16<BUFFER_LOAD_SHORT_D16_HI_OFFEN, BUFFER_LOAD_SHORT_D16_HI_OFFSET, i16, load_private>;
defm : MUBUFScratchLoadPat_Hi16<BUFFER_LOAD_UBYTE_D16_HI_OFFEN, BUFFER_LOAD_UBYTE_D16_HI_OFFSET, i16, az_extloadi8_private>;
defm : MUBUFScratchLoadPat_Hi16<BUFFER_LOAD_SBYTE_D16_HI_OFFEN, BUFFER_LOAD_SBYTE_D16_HI_OFFSET, i16, sextloadi8_private>;
@@ -1489,7 +1489,7 @@ defm : MUBUFScratchStorePat <BUFFER_STOR
defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, BUFFER_STORE_DWORDX4_OFFSET, v4i32, store_private>;
-let OtherPredicates = [HasD16LoadStore] in {
+let OtherPredicates = [D16PreservesUnusedBits] in {
// Hiding the extract high pattern in the PatFrag seems to not
// automatically increase the complexity.
let AddedComplexity = 1 in {
Modified: llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/DSInstructions.td?rev=331551&r1=331550&r2=331551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/DSInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/DSInstructions.td Fri May 4 13:06:57 2018
@@ -655,7 +655,7 @@ defm : DSReadPat_mc <DS_READ_B128, v4i32
} // End AddedComplexity = 100
-let OtherPredicates = [HasD16LoadStore] in {
+let OtherPredicates = [D16PreservesUnusedBits] in {
let AddedComplexity = 100 in {
defm : DSReadPat_Hi16<DS_READ_U16_D16_HI, load_local>;
defm : DSReadPat_Hi16<DS_READ_U8_D16_HI, az_extloadi8_local>;
@@ -689,7 +689,7 @@ defm : DSWritePat_mc <DS_WRITE_B8, i16,
defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">;
defm : DSWritePat_mc <DS_WRITE_B32, i32, "store_local">;
-let OtherPredicates = [HasD16LoadStore] in {
+let OtherPredicates = [D16PreservesUnusedBits] in {
def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_local_hi16>;
def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_local_hi16>;
}
Modified: llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td?rev=331551&r1=331550&r2=331551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td Fri May 4 13:06:57 2018
@@ -780,7 +780,7 @@ def : FlatAtomicPat <FLAT_ATOMIC_XOR_X2_
def : FlatStorePat <FLAT_STORE_BYTE, truncstorei8_flat, i16>;
def : FlatStorePat <FLAT_STORE_SHORT, store_flat, i16>;
-let OtherPredicates = [HasD16LoadStore] in {
+let OtherPredicates = [D16PreservesUnusedBits] in {
def : FlatStorePat <FLAT_STORE_SHORT_D16_HI, truncstorei16_hi16_flat, i32>;
def : FlatStorePat <FLAT_STORE_BYTE_D16_HI, truncstorei8_hi16_flat, i32>;
@@ -824,7 +824,7 @@ def : FlatStoreSignedPat <GLOBAL_STORE_D
def : FlatStoreSignedPat <GLOBAL_STORE_DWORDX2, store_global, v2i32>;
def : FlatStoreSignedPat <GLOBAL_STORE_DWORDX4, store_global, v4i32>;
-let OtherPredicates = [HasD16LoadStore] in {
+let OtherPredicates = [D16PreservesUnusedBits] in {
def : FlatStoreSignedPat <GLOBAL_STORE_SHORT_D16_HI, truncstorei16_hi16_global, i32>;
def : FlatStoreSignedPat <GLOBAL_STORE_BYTE_D16_HI, truncstorei8_hi16_global, i32>;
Modified: llvm/trunk/test/CodeGen/AMDGPU/load-hi16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-hi16.ll?rev=331551&r1=331550&r2=331551&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/load-hi16.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/load-hi16.ll Fri May 4 13:06:57 2018
@@ -1,13 +1,14 @@
-; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900 %s
+; RUN: llc -march=amdgcn -mcpu=gfx906 -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX906,NO-D16-HI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX803,NO-D16-HI %s
; GCN-LABEL: {{^}}load_local_hi_v2i16_undeflo:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_read_u16_d16_hi v0, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: ds_read_u16_d16_hi v0, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: ds_read_u16 v
+; NO-D16-HI: ds_read_u16 v
define <2 x i16> @load_local_hi_v2i16_undeflo(i16 addrspace(3)* %in) #0 {
entry:
%load = load i16, i16 addrspace(3)* %in
@@ -17,12 +18,12 @@ entry:
; GCN-LABEL: {{^}}load_local_hi_v2i16_reglo:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_read_u16_d16_hi v1, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: v_mov_b32_e32 v0, v1
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: ds_read_u16_d16_hi v1, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: v_mov_b32_e32 v0, v1
+; GFX900-NEXT: s_setpc_b64
-; VI: ds_read_u16 v
+; NO-D16-HI: ds_read_u16 v
define <2 x i16> @load_local_hi_v2i16_reglo(i16 addrspace(3)* %in, i16 %reg) #0 {
entry:
%load = load i16, i16 addrspace(3)* %in
@@ -34,13 +35,13 @@ entry:
; Show that we get reasonable regalloc without physreg constraints.
; GCN-LABEL: {{^}}load_local_hi_v2i16_reglo_vreg:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_read_u16_d16_hi v1, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v[0:1], v1, off{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: ds_read_u16_d16_hi v1, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v[0:1], v1, off{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: ds_read_u16 v
+; NO-D16-HI: ds_read_u16 v
define void @load_local_hi_v2i16_reglo_vreg(i16 addrspace(3)* %in, i16 %reg) #0 {
entry:
%load = load i16, i16 addrspace(3)* %in
@@ -52,13 +53,13 @@ entry:
; GCN-LABEL: {{^}}load_local_hi_v2i16_zerolo:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: ds_read_u16_d16_hi v1, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: v_mov_b32_e32 v0, v1
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: ds_read_u16_d16_hi v1, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: v_mov_b32_e32 v0, v1
+; GFX900-NEXT: s_setpc_b64
-; VI: ds_read_u16 v
+; NO-D16-HI: ds_read_u16 v
define <2 x i16> @load_local_hi_v2i16_zerolo(i16 addrspace(3)* %in) #0 {
entry:
%load = load i16, i16 addrspace(3)* %in
@@ -69,13 +70,13 @@ entry:
; FIXME: Remove m0 initialization
; GCN-LABEL: {{^}}load_local_hi_v2i16_zerolo_shift:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_read_u16 v0, v0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: ds_read_u16 v0, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_setpc_b64
-; VI: ds_read_u16 v
-; VI: v_lshlrev_b32_e32 v0, 16, v0
+; NO-D16-HI: ds_read_u16 v
+; NO-D16-HI: v_lshlrev_b32_e32 v0, 16, v0
define i32 @load_local_hi_v2i16_zerolo_shift(i16 addrspace(3)* %in) #0 {
entry:
%load = load i16, i16 addrspace(3)* %in
@@ -86,13 +87,13 @@ entry:
; GCN-LABEL: {{^}}load_local_hi_v2f16_reglo_vreg:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_read_u16_d16_hi v1, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v[0:1], v1, off{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: ds_read_u16_d16_hi v1, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v[0:1], v1, off{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: ds_read_u16 v
+; NO-D16-HI: ds_read_u16 v
define void @load_local_hi_v2f16_reglo_vreg(half addrspace(3)* %in, half %reg) #0 {
entry:
%load = load half, half addrspace(3)* %in
@@ -104,13 +105,13 @@ entry:
; GCN-LABEL: {{^}}load_local_hi_v2i16_reglo_vreg_zexti8:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_read_u8_d16_hi v1, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v[0:1], v1, off{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: ds_read_u8_d16_hi v1, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v[0:1], v1, off{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: ds_read_u8 v
+; NO-D16-HI: ds_read_u8 v
define void @load_local_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(3)* %in, i16 %reg) #0 {
entry:
%load = load i8, i8 addrspace(3)* %in
@@ -123,13 +124,13 @@ entry:
; GCN-LABEL: {{^}}load_local_hi_v2i16_reglo_vreg_sexti8:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_read_i8_d16_hi v1, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v[0:1], v1, off{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: ds_read_i8_d16_hi v1, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v[0:1], v1, off{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: ds_read_i8 v
+; NO-D16-HI: ds_read_i8 v
define void @load_local_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(3)* %in, i16 %reg) #0 {
entry:
%load = load i8, i8 addrspace(3)* %in
@@ -142,11 +143,11 @@ entry:
; GCN-LABEL: {{^}}load_global_hi_v2i16_reglo_vreg:
; GCN: s_waitcnt
-; GFX9-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
define void @load_global_hi_v2i16_reglo_vreg(i16 addrspace(1)* %in, i16 %reg) #0 {
entry:
%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 -2047
@@ -159,11 +160,11 @@ entry:
; GCN-LABEL: {{^}}load_global_hi_v2f16_reglo_vreg:
; GCN: s_waitcnt
-; GFX9-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
define void @load_global_hi_v2f16_reglo_vreg(half addrspace(1)* %in, half %reg) #0 {
entry:
%gep = getelementptr inbounds half, half addrspace(1)* %in, i64 -2047
@@ -176,11 +177,11 @@ entry:
; GCN-LABEL: {{^}}load_global_hi_v2i16_reglo_vreg_zexti8:
; GCN: s_waitcnt
-; GFX9-NEXT: global_load_ubyte_d16_hi v2, v[0:1], off offset:-4095
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: global_load_ubyte_d16_hi v2, v[0:1], off offset:-4095
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
define void @load_global_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(1)* %in, i16 %reg) #0 {
entry:
%gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095
@@ -194,11 +195,11 @@ entry:
; GCN-LABEL: {{^}}load_global_hi_v2i16_reglo_vreg_sexti8:
; GCN: s_waitcnt
-; GFX9-NEXT: global_load_sbyte_d16_hi v2, v[0:1], off offset:-4095
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: global_load_sbyte_d16_hi v2, v[0:1], off offset:-4095
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
define void @load_global_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(1)* %in, i16 %reg) #0 {
entry:
%gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095
@@ -212,15 +213,16 @@ entry:
; GCN-LABEL: load_flat_hi_v2i16_reglo_vreg:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_load_short_d16_hi v2, v[0:1]
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v[0:1], v2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
-
-; VI: flat_load_ushort v{{[0-9]+}}
-; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
-; VI: v_or_b32_sdwa
+; GFX900-NEXT: flat_load_short_d16_hi v2, v[0:1]
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v[0:1], v2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
+
+; NO-D16-HI: flat_load_ushort v{{[0-9]+}}
+; GFX803: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
+; GFX803: v_or_b32_sdwa
+; GFX906: v_lshl_or_b32 v{{[0-9]+}}, v{{[0-9]+}}, 16,
define void @load_flat_hi_v2i16_reglo_vreg(i16* %in, i16 %reg) #0 {
entry:
%load = load i16, i16* %in
@@ -232,15 +234,16 @@ entry:
; GCN-LABEL: {{^}}load_flat_hi_v2f16_reglo_vreg:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_load_short_d16_hi v2, v[0:1]
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v[0:1], v2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
-
-; VI: flat_load_ushort v{{[0-9]+}}
-; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
-; VI: v_or_b32_sdwa
+; GFX900-NEXT: flat_load_short_d16_hi v2, v[0:1]
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v[0:1], v2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
+
+; NO-D16-HI: flat_load_ushort v{{[0-9]+}}
+; GFX803: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
+; GFX803: v_or_b32_sdwa
+; GFX906: v_lshl_or_b32 v{{[0-9]+}}, v{{[0-9]+}}, 16,
define void @load_flat_hi_v2f16_reglo_vreg(half* %in, half %reg) #0 {
entry:
%load = load half, half* %in
@@ -252,15 +255,16 @@ entry:
; GCN-LABEL: {{^}}load_flat_hi_v2i16_reglo_vreg_zexti8:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_load_ubyte_d16_hi v2, v[0:1]
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v[0:1], v2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
-
-; VI: flat_load_ubyte v{{[0-9]+}}
-; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
-; VI: v_or_b32_sdwa
+; GFX900-NEXT: flat_load_ubyte_d16_hi v2, v[0:1]
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v[0:1], v2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
+
+; NO-D16-HI: flat_load_ubyte v{{[0-9]+}}
+; GFX803: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
+; GFX803: v_or_b32_sdwa
+; GFX906: v_lshl_or_b32 v{{[0-9]+}}, v{{[0-9]+}}, 16,
define void @load_flat_hi_v2i16_reglo_vreg_zexti8(i8* %in, i16 %reg) #0 {
entry:
%load = load i8, i8* %in
@@ -273,15 +277,16 @@ entry:
; GCN-LABEL: {{^}}load_flat_hi_v2i16_reglo_vreg_sexti8:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_load_sbyte_d16_hi v2, v[0:1]
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v[0:1], v2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
-
-; VI: flat_load_sbyte v{{[0-9]+}}
-; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
-; VI: v_or_b32_sdwa
+; GFX900-NEXT: flat_load_sbyte_d16_hi v2, v[0:1]
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v[0:1], v2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
+
+; NO-D16-HI: flat_load_sbyte v{{[0-9]+}}
+; GFX803: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
+; GFX803: v_or_b32_sdwa
+; GFX906: v_lshl_or_b32 v{{[0-9]+}}, v{{[0-9]+}}, 16,
define void @load_flat_hi_v2i16_reglo_vreg_sexti8(i8* %in, i16 %reg) #0 {
entry:
%load = load i8, i8* %in
@@ -294,13 +299,13 @@ entry:
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg:
; GCN: s_waitcnt
-; GFX9: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
+; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 {
entry:
%gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2045
@@ -313,13 +318,13 @@ entry:
; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg:
; GCN: s_waitcnt
-; GFX9: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
+; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
define void @load_private_hi_v2f16_reglo_vreg(half addrspace(5)* byval %in, half %reg) #0 {
entry:
%gep = getelementptr inbounds half, half addrspace(5)* %in, i64 2045
@@ -332,13 +337,13 @@ entry:
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff:
; GCN: s_waitcnt
-; GFX9: buffer_load_short_d16_hi v0, off, s[0:3], s4 offset:4094{{$}}
-; GFX9: s_waitcnt
-; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900: buffer_load_short_d16_hi v0, off, s[0:3], s4 offset:4094{{$}}
+; GFX900: s_waitcnt
+; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
+; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval %in, i16 %reg) #0 {
entry:
%load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
@@ -350,13 +355,13 @@ entry:
; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg_nooff:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
+; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2f16_reglo_vreg_nooff(half addrspace(5)* %in, half %reg) #0 {
entry:
%load = load volatile half, half addrspace(5)* inttoptr (i32 4094 to half addrspace(5)*)
@@ -368,13 +373,13 @@ entry:
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_zexti8:
; GCN: s_waitcnt
-; GFX9: buffer_load_ubyte_d16_hi v0, off, s[0:3], s5 offset:4095{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900: buffer_load_ubyte_d16_hi v0, off, s[0:3], s5 offset:4095{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}}
+; NO-D16-HI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}}
define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 {
entry:
%gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4091
@@ -388,13 +393,13 @@ entry:
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_sexti8:
; GCN: s_waitcnt
-; GFX9: buffer_load_sbyte_d16_hi v0, off, s[0:3], s5 offset:4095{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900: buffer_load_sbyte_d16_hi v0, off, s[0:3], s5 offset:4095{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}}
+; NO-D16-HI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}}
define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 {
entry:
%gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4091
@@ -408,13 +413,13 @@ entry:
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff_zexti8:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
+; NO-D16-HI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry:
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
@@ -427,13 +432,13 @@ entry:
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff_sexti8:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_load_sbyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: buffer_load_sbyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: buffer_load_sbyte v0, off, s[0:3], s4 offset:4094{{$}}
+; NO-D16-HI: buffer_load_sbyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff_sexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry:
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
@@ -446,13 +451,13 @@ entry:
; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg_nooff_zexti8:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
+; NO-D16-HI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2f16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, half %reg) #0 {
entry:
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
@@ -466,13 +471,14 @@ entry:
; GCN-LABEL: {{^}}load_constant_hi_v2i16_reglo_vreg:
; GCN: s_waitcnt
-; GFX9-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: flat_load_ushort
+; GFX803: flat_load_ushort
+; GFX906: global_load_ushort
define void @load_constant_hi_v2i16_reglo_vreg(i16 addrspace(4)* %in, i16 %reg) #0 {
entry:
%gep = getelementptr inbounds i16, i16 addrspace(4)* %in, i64 -2047
@@ -485,13 +491,14 @@ entry:
; GCN-LABEL: load_constant_hi_v2f16_reglo_vreg
; GCN: s_waitcnt
-; GFX9-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_store_dword
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_store_dword
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
-; VI: flat_load_ushort
+; GFX803: flat_load_ushort
+; GFX906: global_load_ushort
define void @load_constant_hi_v2f16_reglo_vreg(half addrspace(4)* %in, half %reg) #0 {
entry:
%gep = getelementptr inbounds half, half addrspace(4)* %in, i64 -2047
@@ -506,8 +513,8 @@ entry:
; to offset variant.
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_to_offset:
-; GFX9: buffer_store_dword
-; GFX9-NEXT: buffer_load_short_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4094
+; GFX900: buffer_store_dword
+; GFX900-NEXT: buffer_load_short_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4094
define void @load_private_hi_v2i16_reglo_vreg_to_offset(i16 %reg) #0 {
entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5)
@@ -523,8 +530,8 @@ entry:
}
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_sexti8_to_offset:
-; GFX9: buffer_store_dword
-; GFX9-NEXT: buffer_load_sbyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095
+; GFX900: buffer_store_dword
+; GFX900-NEXT: buffer_load_sbyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095
define void @load_private_hi_v2i16_reglo_vreg_sexti8_to_offset(i16 %reg) #0 {
entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5)
@@ -541,8 +548,8 @@ entry:
}
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_zexti8_to_offset:
-; GFX9: buffer_store_dword
-; GFX9-NEXT: buffer_load_ubyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095
+; GFX900: buffer_store_dword
+; GFX900-NEXT: buffer_load_ubyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095
define void @load_private_hi_v2i16_reglo_vreg_zexti8_to_offset(i16 %reg) #0 {
entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5)
@@ -562,12 +569,12 @@ entry:
; FIXME: Is there a cost to using the extload over not?
; GCN-LABEL: {{^}}load_local_v2i16_split:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_read_u16 v1, v0
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: ds_read_u16_d16_hi v1, v0 offset:2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: v_mov_b32_e32 v0, v1
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: ds_read_u16 v1, v0
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: ds_read_u16_d16_hi v1, v0 offset:2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: v_mov_b32_e32 v0, v1
+; GFX900-NEXT: s_setpc_b64
define <2 x i16> @load_local_v2i16_split(i16 addrspace(3)* %in) #0 {
entry:
%gep = getelementptr inbounds i16, i16 addrspace(3)* %in, i32 1
@@ -581,12 +588,12 @@ entry:
; FIXME: Remove waitcnt between reads
; GCN-LABEL: {{^}}load_global_v2i16_split:
; GCN: s_waitcnt
-; GFX9-NEXT: global_load_ushort v2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_load_short_d16_hi v2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: v_mov_b32_e32 v0, v2
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: global_load_ushort v2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_load_short_d16_hi v2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: v_mov_b32_e32 v0, v2
+; GFX900-NEXT: s_setpc_b64
define <2 x i16> @load_global_v2i16_split(i16 addrspace(1)* %in) #0 {
entry:
%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 1
@@ -600,12 +607,12 @@ entry:
; FIXME: Remove waitcnt between reads
; GCN-LABEL: {{^}}load_flat_v2i16_split:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_load_ushort v2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: flat_load_short_d16_hi v2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: v_mov_b32_e32 v0, v2
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: flat_load_ushort v2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: flat_load_short_d16_hi v2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: v_mov_b32_e32 v0, v2
+; GFX900-NEXT: s_setpc_b64
define <2 x i16> @load_flat_v2i16_split(i16* %in) #0 {
entry:
%gep = getelementptr inbounds i16, i16* %in, i64 1
@@ -619,12 +626,12 @@ entry:
; FIXME: Remove waitcnt between reads
; GCN-LABEL: {{^}}load_constant_v2i16_split:
; GCN: s_waitcnt
-; GFX9-NEXT: global_load_ushort v2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: global_load_short_d16_hi v2
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: v_mov_b32_e32 v0, v2
-; GFX9-NEXT: s_setpc_b64
+; GFX900-NEXT: global_load_ushort v2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: global_load_short_d16_hi v2
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: v_mov_b32_e32 v0, v2
+; GFX900-NEXT: s_setpc_b64
define <2 x i16> @load_constant_v2i16_split(i16 addrspace(4)* %in) #0 {
entry:
%gep = getelementptr inbounds i16, i16 addrspace(4)* %in, i64 1
@@ -639,11 +646,11 @@ entry:
; FIXME: Is there a cost to using the extload over not?
; GCN-LABEL: {{^}}load_private_v2i16_split:
; GCN: s_waitcnt
-; GFX9: buffer_load_ushort v0, off, s[0:3], s5 offset:4{{$}}
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:6
-; GFX9-NEXT: s_waitcnt
-; GFX9-NEXT: s_setpc_b64
+; GFX900: buffer_load_ushort v0, off, s[0:3], s5 offset:4{{$}}
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:6
+; GFX900-NEXT: s_waitcnt
+; GFX900-NEXT: s_setpc_b64
define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval %in) #0 {
entry:
%gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i32 1
Modified: llvm/trunk/test/CodeGen/AMDGPU/store-hi16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/store-hi16.ll?rev=331551&r1=331550&r2=331551&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/store-hi16.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/store-hi16.ll Fri May 4 13:06:57 2018
@@ -1,13 +1,15 @@
-; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900 %s
+; RUN: llc -march=amdgcn -mcpu=gfx906 -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX906,NO-D16-HI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX803,NO-D16-HI %s
; GCN-LABEL: {{^}}store_global_hi_v2i16:
; GCN: s_waitcnt
-; GFX9-NEXT: global_store_short_d16_hi v[0:1], v2, off
+; GFX900-NEXT: global_store_short_d16_hi v[0:1], v2, off
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: flat_store_short v[0:1], v2
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803-NEXT: flat_store_short v[0:1], v2
+; GFX906-NEXT: global_store_short v[0:1], v2, off
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -23,10 +25,11 @@ entry:
; GCN-LABEL: {{^}}store_global_hi_v2f16:
; GCN: s_waitcnt
-; GFX9-NEXT: global_store_short_d16_hi v[0:1], v2, off
+; GFX900-NEXT: global_store_short_d16_hi v[0:1], v2, off
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: flat_store_short v[0:1], v2
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803-NEXT: flat_store_short v[0:1], v2
+; GFX906-NEXT: global_store_short v[0:1], v2, off
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -42,10 +45,11 @@ entry:
; GCN-LABEL: {{^}}store_global_hi_i32_shift:
; GCN: s_waitcnt
-; GFX9-NEXT: global_store_short_d16_hi v[0:1], v2, off
+; GFX900-NEXT: global_store_short_d16_hi v[0:1], v2, off
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: flat_store_short v[0:1], v2
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803-NEXT: flat_store_short v[0:1], v2
+; GFX906-NEXT: global_store_short v[0:1], v2, off
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -60,10 +64,11 @@ entry:
; GCN-LABEL: {{^}}store_global_hi_v2i16_i8:
; GCN: s_waitcnt
-; GFX9-NEXT: global_store_byte_d16_hi v[0:1], v2, off
+; GFX900-NEXT: global_store_byte_d16_hi v[0:1], v2, off
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: flat_store_byte v[0:1], v2
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803-NEXT: flat_store_byte v[0:1], v2
+; GFX906-NEXT: global_store_byte v[0:1], v2, off
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -79,10 +84,11 @@ entry:
; GCN-LABEL: {{^}}store_global_hi_i8_shift:
; GCN: s_waitcnt
-; GFX9-NEXT: global_store_byte_d16_hi v[0:1], v2, off
+; GFX900-NEXT: global_store_byte_d16_hi v[0:1], v2, off
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: flat_store_byte v[0:1], v2
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803-NEXT: flat_store_byte v[0:1], v2
+; GFX906-NEXT: global_store_byte v[0:1], v2, off
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -96,13 +102,16 @@ entry:
; GCN-LABEL: {{^}}store_global_hi_v2i16_max_offset:
; GCN: s_waitcnt
-; GFX9-NEXT: global_store_short_d16_hi v[0:1], v2, off offset:4094
+; GFX900-NEXT: global_store_short_d16_hi v[0:1], v2, off offset:4094
-; VI-DAG: v_add_u32_e32
-; VI-DAG: v_addc_u32_e32
-; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803-DAG: v_add_u32_e32
+; GFX803-DAG: v_addc_u32_e32
+; GFX803-DAG: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803: flat_store_short v[0:1], v2{{$}}
+
+; GFX906-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX906-NEXT: global_store_short v[0:1], v2, off
-; VI: flat_store_short v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
define void @store_global_hi_v2i16_max_offset(i16 addrspace(1)* %out, i32 %arg) #0 {
@@ -117,13 +126,16 @@ entry:
; GCN-LABEL: {{^}}store_global_hi_v2i16_min_offset:
; GCN: s_waitcnt
-; GFX9-NEXT: global_store_short_d16_hi v[0:1], v2, off offset:-4096{{$}}
+; GFX900-NEXT: global_store_short_d16_hi v[0:1], v2, off offset:-4096{{$}}
+
+; GFX803-DAG: v_add_u32_e32
+; GFX803-DAG: v_addc_u32_e32
+; GFX803-DAG: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803: flat_store_short v[0:1], v{{[0-9]$}}
-; VI-DAG: v_add_u32_e32
-; VI-DAG: v_addc_u32_e32
-; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2
+; GFX906-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX906-NEXT: global_store_short v[0:1], v2, off
-; VI: flat_store_short v[0:1], v{{[0-9]$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
define void @store_global_hi_v2i16_min_offset(i16 addrspace(1)* %out, i32 %arg) #0 {
@@ -137,12 +149,15 @@ entry:
; GCN-LABEL: {{^}}store_global_hi_v2i16_i8_max_offset:
; GCN: s_waitcnt
-; GFX9-NEXT: global_store_byte_d16_hi v[0:1], v2, off offset:4095
+; GFX900-NEXT: global_store_byte_d16_hi v[0:1], v2, off offset:4095
+
+; GFX803-DAG: v_add_u32_e32
+; GFX803-DAG: v_addc_u32_e32
+; GFX803-DAG: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803: flat_store_byte v[0:1], v{{[0-9]$}}
-; VI-DAG: v_add_u32_e32
-; VI-DAG: v_addc_u32_e32
-; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2
-; VI: flat_store_byte v[0:1], v{{[0-9]$}}
+; GFX906-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX906-NEXT: global_store_byte v[0:1], v2, off
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -158,13 +173,16 @@ entry:
; GCN-LABEL: {{^}}store_global_hi_v2i16_i8_min_offset:
; GCN: s_waitcnt
-; GFX9-NEXT: global_store_byte_d16_hi v[0:1], v2, off offset:-4095
+; GFX900-NEXT: global_store_byte_d16_hi v[0:1], v2, off offset:-4095
-; VI-DAG: v_add_u32_e32
-; VI-DAG: v_addc_u32_e32
-; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803-DAG: v_add_u32_e32
+; GFX803-DAG: v_addc_u32_e32
+; GFX803-DAG: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803: flat_store_byte v[0:1], v{{[0-9]$}}
+
+; GFX906-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX906-NEXT: global_store_byte v[0:1], v2, off
-; VI: flat_store_byte v[0:1], v{{[0-9]$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
define void @store_global_hi_v2i16_i8_min_offset(i8 addrspace(1)* %out, i32 %arg) #0 {
@@ -180,10 +198,10 @@ entry:
; GCN-LABEL: {{^}}store_flat_hi_v2i16:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
+; GFX900-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: flat_store_short v[0:1], v2
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; NO-D16-HI-NEXT: flat_store_short v[0:1], v2
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -198,10 +216,10 @@ entry:
; GCN-LABEL: {{^}}store_flat_hi_v2f16:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
+; GFX900-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: flat_store_short v[0:1], v2
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; NO-D16-HI-NEXT: flat_store_short v[0:1], v2
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -216,10 +234,10 @@ entry:
; GCN-LABEL: {{^}}store_flat_hi_i32_shift:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
+; GFX900-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: flat_store_short v[0:1], v2
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; NO-D16-HI-NEXT: flat_store_short v[0:1], v2
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -234,10 +252,10 @@ entry:
; GCN-LABEL: {{^}}store_flat_hi_v2i16_i8:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}}
+; GFX900-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}}
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: flat_store_byte v[0:1], v2
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; NO-D16-HI-NEXT: flat_store_byte v[0:1], v2
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -253,10 +271,10 @@ entry:
; GCN-LABEL: {{^}}store_flat_hi_i8_shift:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}}
+; GFX900-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}}
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: flat_store_byte v[0:1], v2
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; NO-D16-HI-NEXT: flat_store_byte v[0:1], v2
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -270,12 +288,16 @@ entry:
; GCN-LABEL: {{^}}store_flat_hi_v2i16_max_offset:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2 offset:4094{{$}}
+; GFX900-NEXT: flat_store_short_d16_hi v[0:1], v2 offset:4094{{$}}
+
+; GFX906-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX906-NEXT: flat_store_short v[0:1], v2 offset:4094
+
+; GFX803-DAG: v_add_u32_e32
+; GFX803-DAG: v_addc_u32_e32
+; GFX803-DAG: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803: flat_store_short v[0:1], v2{{$}}
-; VI-DAG: v_add_u32_e32
-; VI-DAG: v_addc_u32_e32
-; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2
-; VI: flat_store_short v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_max_offset(i16* %out, i32 %arg) #0 {
@@ -290,11 +312,16 @@ entry:
; GCN-LABEL: {{^}}store_flat_hi_v2i16_neg_offset:
; GCN: s_waitcnt
; GCN: v_add{{(_co)?}}_{{i|u}}32_e32
-; VI: v_addc_u32_e32
-; GFX9: v_addc_co_u32_e32
-; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
-; VI: flat_store_short v[0:1], v2{{$}}
+; GFX803: v_addc_u32_e32
+; GFX900: v_addc_co_u32_e32
+
+; GFX906-NEXT: v_lshrrev_b32_e32
+; GFX906-NEXT: v_addc_co_u32_e32
+; GFX906: flat_store_short v[0:1], v2
+
+; GFX900-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
+; GFX803: flat_store_short v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_neg_offset(i16* %out, i32 %arg) #0 {
@@ -308,12 +335,16 @@ entry:
; GCN-LABEL: {{^}}store_flat_hi_v2i16_i8_max_offset:
; GCN: s_waitcnt
-; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2 offset:4095{{$}}
+; GFX900-NEXT: flat_store_byte_d16_hi v[0:1], v2 offset:4095{{$}}
+
+; GFX803-DAG: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803-DAG: v_add_u32_e32
+; GFX803-DAG: v_addc_u32_e32
+; GFX803: flat_store_byte v[0:1], v2{{$}}
+
+; GFX906-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX906-NEXT: flat_store_byte v[0:1], v2 offset:4095{{$}}
-; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2
-; VI-DAG: v_add_u32_e32
-; VI-DAG: v_addc_u32_e32
-; VI: flat_store_byte v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_i8_max_offset(i8* %out, i32 %arg) #0 {
@@ -329,12 +360,20 @@ entry:
; GCN-LABEL: {{^}}store_flat_hi_v2i16_i8_neg_offset:
; GCN: s_waitcnt
; GCN-DAG: v_add{{(_co)?}}_{{i|u}}32_e32
-; VI-DAG: v_addc_u32_e32
-; GFX9-DAG: v_addc_co_u32_e32
-; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}}
-; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2
-; VI: flat_store_byte v[0:1], v2{{$}}
+; GFX803-DAG: v_addc_u32_e32
+; GFX900-DAG: v_addc_co_u32_e32
+; GFX906-DAG: v_add_co_u32_e32
+
+; GFX900-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}}
+
+; GFX906-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX906-NEXT: v_addc_co_u32_e32
+; GFX906-NEXT: flat_store_byte v[0:1], v2{{$}}
+
+; GFX803-DAG: v_lshrrev_b32_e32 v2, 16, v2
+; GFX803: flat_store_byte v[0:1], v2{{$}}
+
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_i8_neg_offset(i8* %out, i32 %arg) #0 {
@@ -350,10 +389,10 @@ entry:
; GCN-LABEL: {{^}}store_private_hi_v2i16:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}}
+; GFX900-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}}
-; VI: v_lshrrev_b32_e32 v1, 16, v1
-; VI: buffer_store_short v1, v0, s[0:3], s4 offen{{$}}
+; NO-D16-HI: v_lshrrev_b32_e32 v1, 16, v1
+; NO-D16-HI: buffer_store_short v1, v0, s[0:3], s4 offen{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -369,10 +408,10 @@ entry:
; GCN-LABEL: {{^}}store_private_hi_v2f16:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}}
+; GFX900-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}}
-; VI: v_lshrrev_b32_e32 v1, 16, v1
-; VI: buffer_store_short v1, v0, s[0:3], s4 offen{{$}}
+; NO-D16-HI: v_lshrrev_b32_e32 v1, 16, v1
+; NO-D16-HI: buffer_store_short v1, v0, s[0:3], s4 offen{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -388,10 +427,10 @@ entry:
; GCN-LABEL: {{^}}store_private_hi_i32_shift:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}}
+; GFX900-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}}
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: buffer_store_short v1, v0, s[0:3], s4 offen{{$}}
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; NO-D16-HI-NEXT: buffer_store_short v1, v0, s[0:3], s4 offen{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -406,10 +445,10 @@ entry:
; GCN-LABEL: {{^}}store_private_hi_v2i16_i8:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], s4 offen{{$}}
+; GFX900-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], s4 offen{{$}}
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: buffer_store_byte v1, v0, s[0:3], s4 offen{{$}}
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; NO-D16-HI-NEXT: buffer_store_byte v1, v0, s[0:3], s4 offen{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -425,10 +464,10 @@ entry:
; GCN-LABEL: {{^}}store_private_hi_i8_shift:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], s4 offen{{$}}
+; GFX900-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], s4 offen{{$}}
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: buffer_store_byte v1, v0, s[0:3], s4 offen{{$}}
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; NO-D16-HI-NEXT: buffer_store_byte v1, v0, s[0:3], s4 offen{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -442,10 +481,10 @@ entry:
; GCN-LABEL: {{^}}store_private_hi_v2i16_max_offset:
; GCN: s_waitcnt
-; GFX9: buffer_store_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}}
+; GFX900: buffer_store_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}}
-; VI: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: buffer_store_short v0, off, s[0:3], s5 offset:4094{{$}}
+; NO-D16-HI: v_lshrrev_b32_e32 v0, 16, v0
+; NO-D16-HI-NEXT: buffer_store_short v0, off, s[0:3], s5 offset:4094{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -463,10 +502,10 @@ entry:
; GCN-LABEL: {{^}}store_private_hi_v2i16_nooff:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s4{{$}}
+; GFX900-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s4{{$}}
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: buffer_store_short v0, off, s[0:3], s4{{$}}
+; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; NO-D16-HI-NEXT: buffer_store_short v0, off, s[0:3], s4{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -483,10 +522,10 @@ entry:
; GCN-LABEL: {{^}}store_private_hi_v2i16_i8_nooff:
; GCN: s_waitcnt
-; GFX9-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s4{{$}}
+; GFX900-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s4{{$}}
-; VI: v_lshrrev_b32_e32 v0, 16, v0
-; VI: buffer_store_byte v0, off, s[0:3], s4{{$}}
+; NO-D16-HI: v_lshrrev_b32_e32 v0, 16, v0
+; NO-D16-HI: buffer_store_byte v0, off, s[0:3], s4{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -502,10 +541,10 @@ entry:
; GCN-LABEL: {{^}}store_local_hi_v2i16:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_write_b16_d16_hi v0, v1{{$}}
+; GFX900-NEXT: ds_write_b16_d16_hi v0, v1{{$}}
-; VI: v_lshrrev_b32_e32 v1, 16, v1
-; VI: ds_write_b16 v0, v1
+; NO-D16-HI: v_lshrrev_b32_e32 v1, 16, v1
+; NO-D16-HI: ds_write_b16 v0, v1
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -521,10 +560,10 @@ entry:
; GCN-LABEL: {{^}}store_local_hi_v2f16:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_write_b16_d16_hi v0, v1{{$}}
+; GFX900-NEXT: ds_write_b16_d16_hi v0, v1{{$}}
-; VI: v_lshrrev_b32_e32 v1, 16, v1
-; VI: ds_write_b16 v0, v1
+; NO-D16-HI: v_lshrrev_b32_e32 v1, 16, v1
+; NO-D16-HI: ds_write_b16 v0, v1
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -540,10 +579,10 @@ entry:
; GCN-LABEL: {{^}}store_local_hi_i32_shift:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_write_b16_d16_hi v0, v1{{$}}
+; GFX900-NEXT: ds_write_b16_d16_hi v0, v1{{$}}
-; VI: v_lshrrev_b32_e32 v1, 16, v1
-; VI: ds_write_b16 v0, v1
+; NO-D16-HI: v_lshrrev_b32_e32 v1, 16, v1
+; NO-D16-HI: ds_write_b16 v0, v1
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -558,10 +597,10 @@ entry:
; GCN-LABEL: {{^}}store_local_hi_v2i16_i8:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_write_b8_d16_hi v0, v1{{$}}
+; GFX900-NEXT: ds_write_b8_d16_hi v0, v1{{$}}
-; VI: v_lshrrev_b32_e32 v1, 16, v1
-; VI: ds_write_b8 v0, v1
+; NO-D16-HI: v_lshrrev_b32_e32 v1, 16, v1
+; NO-D16-HI: ds_write_b8 v0, v1
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -576,10 +615,10 @@ entry:
; GCN-LABEL: {{^}}store_local_hi_v2i16_max_offset:
; GCN: s_waitcnt
-; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:65534{{$}}
+; GFX900-NEXT: ds_write_b16_d16_hi v0, v1 offset:65534{{$}}
-; VI: v_lshrrev_b32_e32 v1, 16, v1
-; VI: ds_write_b16 v0, v1 offset:65534{{$}}
+; NO-D16-HI: v_lshrrev_b32_e32 v1, 16, v1
+; NO-D16-HI: ds_write_b16 v0, v1 offset:65534{{$}}
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
@@ -595,8 +634,8 @@ entry:
; GCN-LABEL: {{^}}store_private_hi_v2i16_to_offset:
; GCN: s_waitcnt
-; GFX9: buffer_store_dword
-; GFX9-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s5 offset:4094
+; GFX900: buffer_store_dword
+; GFX900-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s5 offset:4094
define void @store_private_hi_v2i16_to_offset(i32 %arg) #0 {
entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5)
@@ -612,8 +651,8 @@ entry:
; GCN-LABEL: {{^}}store_private_hi_v2i16_i8_to_offset:
; GCN: s_waitcnt
-; GFX9: buffer_store_dword
-; GFX9-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s5 offset:4095
+; GFX900: buffer_store_dword
+; GFX900-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s5 offset:4095
define void @store_private_hi_v2i16_i8_to_offset(i32 %arg) #0 {
entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5)
Modified: llvm/trunk/test/MC/AMDGPU/gfx9_asm_all.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/gfx9_asm_all.s?rev=331551&r1=331550&r2=331551&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/gfx9_asm_all.s (original)
+++ llvm/trunk/test/MC/AMDGPU/gfx9_asm_all.s Fri May 4 13:06:57 2018
@@ -1,4 +1,5 @@
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -mattr=+d16-preserves-unused-bits -show-encoding %s | FileCheck %s
ds_add_u32 v1, v2 offset:65535
// CHECK: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
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