[PATCH] D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.

[Clement Courbet via Phabricator via llvm-commits]

courbet added inline comments.


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Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:376
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [5]; }
+                                                    let ResourceCycles = [5, 1]; }
 def M3WriteVLDG    : SchedWriteRes<[M3UnitL,
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This still feels weirdly asymetric. Is that correct ?


Repository:
  rL LLVM

https://reviews.llvm.org/D46356