[llvm] r331488 - [X86][Znver1] Use SchedAlias to tag microcoded scheduler classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu May 3 15:12:23 PDT 2018
Author: rksimon
Date: Thu May 3 15:12:23 2018
New Revision: 331488
URL: http://llvm.org/viewvc/llvm-project?rev=331488&view=rev
Log:
[X86][Znver1] Use SchedAlias to tag microcoded scheduler classes
Avoids extra entries in the class tables.
Found a typo that missed the MMX_PHSUBSW instruction.
Modified:
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
llvm/trunk/test/CodeGen/X86/mmx-schedule.ll
llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-ssse3.s
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=331488&r1=331487&r2=331488&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Thu May 3 15:12:23 2018
@@ -191,8 +191,6 @@ def : WriteRes<WriteFStore,
def : WriteRes<WriteFMove, [ZnFPU]>;
def : WriteRes<WriteFLoad, [ZnAGU]> { let Latency = 8; }
-defm : ZnWriteResFpuPair<WriteFHAdd, [ZnFPU0], 3>;
-defm : ZnWriteResFpuPair<WriteFHAddY, [ZnFPU0], 3>;
defm : ZnWriteResFpuPair<WriteFAdd, [ZnFPU0], 3>;
defm : ZnWriteResFpuPair<WriteFAddY, [ZnFPU0], 3>;
defm : ZnWriteResFpuPair<WriteFCmp, [ZnFPU0], 3>;
@@ -241,8 +239,6 @@ defm : ZnWriteResFpuPair<WriteVecShiftIm
defm : ZnWriteResFpuPair<WriteVecShiftImmY, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecLogic, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecLogicY, [ZnFPU], 1>;
-defm : ZnWriteResFpuPair<WritePHAdd, [ZnFPU], 1>;
-defm : ZnWriteResFpuPair<WritePHAddY, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecALU, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecALUY, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecIMul, [ZnFPU0], 4>;
@@ -297,26 +293,28 @@ defm : ZnWriteResFpuPair<WriteFShuffle25
defm : ZnWriteResFpuPair<WriteFVarShuffle256, [ZnFPU], 100>;
// Microcoded Instructions
-let Latency = 100 in {
- def : WriteRes<WriteMicrocoded, []>;
- def : WriteRes<WriteSystem, []>;
- def : WriteRes<WriteMPSAD, []>;
- def : WriteRes<WriteMPSADY, []>;
- def : WriteRes<WriteMPSADLd, []>;
- def : WriteRes<WriteMPSADYLd, []>;
- def : WriteRes<WriteCLMul, []>;
- def : WriteRes<WriteCLMulLd, []>;
- def : WriteRes<WritePCmpIStrM, []>;
- def : WriteRes<WritePCmpIStrMLd, []>;
- def : WriteRes<WritePCmpEStrI, []>;
- def : WriteRes<WritePCmpEStrILd, []>;
- def : WriteRes<WritePCmpEStrM, []>;
- def : WriteRes<WritePCmpEStrMLd, []>;
- def : WriteRes<WritePCmpIStrI, []>;
- def : WriteRes<WritePCmpIStrILd, []>;
- def : WriteRes<WriteLDMXCSR, []>;
- def : WriteRes<WriteSTMXCSR, []>;
- }
+def ZnWriteMicrocoded : SchedWriteRes<[]> {
+ let Latency = 100;
+}
+
+def : SchedAlias<WriteMicrocoded, ZnWriteMicrocoded>;
+def : SchedAlias<WriteSystem, ZnWriteMicrocoded>;
+def : SchedAlias<WriteMPSAD, ZnWriteMicrocoded>;
+def : SchedAlias<WriteMPSADY, ZnWriteMicrocoded>;
+def : SchedAlias<WriteMPSADLd, ZnWriteMicrocoded>;
+def : SchedAlias<WriteMPSADYLd, ZnWriteMicrocoded>;
+def : SchedAlias<WriteCLMul, ZnWriteMicrocoded>;
+def : SchedAlias<WriteCLMulLd, ZnWriteMicrocoded>;
+def : SchedAlias<WritePCmpIStrM, ZnWriteMicrocoded>;
+def : SchedAlias<WritePCmpIStrMLd, ZnWriteMicrocoded>;
+def : SchedAlias<WritePCmpEStrI, ZnWriteMicrocoded>;
+def : SchedAlias<WritePCmpEStrILd, ZnWriteMicrocoded>;
+def : SchedAlias<WritePCmpEStrM, ZnWriteMicrocoded>;
+def : SchedAlias<WritePCmpEStrMLd, ZnWriteMicrocoded>;
+def : SchedAlias<WritePCmpIStrI, ZnWriteMicrocoded>;
+def : SchedAlias<WritePCmpIStrILd, ZnWriteMicrocoded>;
+def : SchedAlias<WriteLDMXCSR, ZnWriteMicrocoded>;
+def : SchedAlias<WriteSTMXCSR, ZnWriteMicrocoded>;
//=== Regex based InstRW ===//
// Notation:
@@ -1028,13 +1026,10 @@ def : InstRW<[WriteMicrocoded], (instreg
// HADD, HSUB PS/PD
// PHADD|PHSUB (S) W/D.
-def : InstRW<[WriteMicrocoded], (instregex "MMX_PHADD(W|D)r(r|m)",
- "MMX_PHADDSWr(r|m)",
- "MMX_PHSUB(W|D)r(r|m)",
- "MMX_PHSUBSWrr",
- "(V?)PH(ADD|SUB)(W|D)(Y?)r(r|m)",
- "(V?)PH(ADD|SUB)SW(Y?)r(r|m)")>;
-
+def : SchedAlias<WritePHAdd, ZnWriteMicrocoded>;
+def : SchedAlias<WritePHAddLd, ZnWriteMicrocoded>;
+def : SchedAlias<WritePHAddY, ZnWriteMicrocoded>;
+def : SchedAlias<WritePHAddYLd, ZnWriteMicrocoded>;
// PCMPGTQ.
def ZnWritePCMPGTQr : SchedWriteRes<[ZnFPU03]>;
@@ -1452,7 +1447,10 @@ def : InstRW<[ZnWriteSHA256RNDS2Ld], (in
//-- Arithmetic instructions --//
// HADD, HSUB PS/PD
-def : InstRW<[WriteMicrocoded], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)r(r|m)")>;
+def : SchedAlias<WriteFHAdd, ZnWriteMicrocoded>;
+def : SchedAlias<WriteFHAddLd, ZnWriteMicrocoded>;
+def : SchedAlias<WriteFHAddY, ZnWriteMicrocoded>;
+def : SchedAlias<WriteFHAddYLd, ZnWriteMicrocoded>;
// MULL SS/SD PS/PD.
// x,x / v,v,v.
Modified: llvm/trunk/test/CodeGen/X86/mmx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-schedule.ll?rev=331488&r1=331487&r2=331488&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mmx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mmx-schedule.ll Thu May 3 15:12:23 2018
@@ -3409,7 +3409,7 @@ define i64 @test_phsubsw(x86_mmx %a0, x8
; ZNVER1-LABEL: test_phsubsw:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: phsubsw %mm1, %mm0 # sched: [100:?]
-; ZNVER1-NEXT: phsubsw (%rdi), %mm0 # sched: [8:0.50]
+; ZNVER1-NEXT: phsubsw (%rdi), %mm0 # sched: [100:?]
; ZNVER1-NEXT: movq %mm0, %rax # sched: [2:1.00]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call x86_mmx @llvm.x86.ssse3.phsub.sw(x86_mmx %a0, x86_mmx %a1)
Modified: llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-ssse3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-ssse3.s?rev=331488&r1=331487&r2=331488&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-ssse3.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-ssse3.s Thu May 3 15:12:23 2018
@@ -139,7 +139,7 @@ psignw (%rax), %xmm2
# CHECK-NEXT: 1 100 - phsubd %xmm0, %xmm2
# CHECK-NEXT: 1 100 - * phsubd (%rax), %xmm2
# CHECK-NEXT: 1 100 - phsubsw %mm0, %mm2
-# CHECK-NEXT: 1 8 0.50 * phsubsw (%rax), %mm2
+# CHECK-NEXT: 1 100 - * phsubsw (%rax), %mm2
# CHECK-NEXT: 1 100 - phsubsw %xmm0, %xmm2
# CHECK-NEXT: 1 100 - * phsubsw (%rax), %xmm2
# CHECK-NEXT: 1 100 - phsubw %mm0, %mm2
@@ -187,7 +187,7 @@ psignw (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
-# CHECK-NEXT: 10.50 10.50 - - - - - 16.25 8.25 8.25 8.25 -
+# CHECK-NEXT: 10.00 10.00 - - - - - 16.00 8.00 8.00 8.00 -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
@@ -224,7 +224,7 @@ psignw (%rax), %xmm2
# CHECK-NEXT: - - - - - - - - - - - - phsubd %xmm0, %xmm2
# CHECK-NEXT: - - - - - - - - - - - - phsubd (%rax), %xmm2
# CHECK-NEXT: - - - - - - - - - - - - phsubsw %mm0, %mm2
-# CHECK-NEXT: 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - phsubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - phsubsw (%rax), %mm2
# CHECK-NEXT: - - - - - - - - - - - - phsubsw %xmm0, %xmm2
# CHECK-NEXT: - - - - - - - - - - - - phsubsw (%rax), %xmm2
# CHECK-NEXT: - - - - - - - - - - - - phsubw %mm0, %mm2
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