[PATCH] D45991: GlobalISel: Use a callback to compute constrained reg class for unallocatble registers
Tom Stellard via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 3 14:48:15 PDT 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL331485: GlobalISel: Use a callback to compute constrained reg class for unallocatbleā¦ (authored by tstellar, committed by ).
Repository:
rL LLVM
https://reviews.llvm.org/D45991
Files:
llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp
Index: llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
===================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
+++ llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -995,6 +995,12 @@
/// of the set as well.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
+
+ virtual const TargetRegisterClass *
+ getConstrainedRegClassForOperand(const MachineOperand &MO,
+ const MachineRegisterInfo &MRI) const {
+ return nullptr;
+ }
};
//===----------------------------------------------------------------------===//
Index: llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp
+++ llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp
@@ -58,6 +58,13 @@
// register class constraints on some of their operands: If it's a use, we can
// skip constraining as the instruction defining the register would constrain
// it.
+
+ // We can't constrain unallocatable register classes, because we can't create
+ // virtual registers for these classes, so we need to let targets handled this
+ // case.
+ if (RegClass && !RegClass->isAllocatable())
+ RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
+
if (!RegClass) {
assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
"Register class constraint is required unless either the "
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