[llvm] r331473 - [X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not SchedWriteVecALU.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu May  3 11:22:49 2018
New Revision: 331473

URL: http://llvm.org/viewvc/llvm-project?rev=331473&view=rev
Log:
[X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not SchedWriteVecALU.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrAVX512.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td

Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=331473&r1=331472&r2=331473&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Thu May  3 11:22:49 2018
@@ -9842,9 +9842,8 @@ multiclass avx512_unary_lowering<string
   }
 }
 
-// FIXME: Is there a better scheduler class for VPLZCNT?
 defm VPLZCNT    : avx512_unary_rm_vl_dq<0x44, 0x44, "vplzcnt", ctlz,
-                                        SchedWriteVecALU, HasCDI>;
+                                        SchedWriteVecIMul, HasCDI>;
 
 // FIXME: Is there a better scheduler class for VPCONFLICT?
 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict,

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=331473&r1=331472&r2=331473&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Thu May  3 11:22:49 2018
@@ -1249,13 +1249,7 @@ def: InstRW<[SKXWriteResGroup50], (instr
                                              "VCVTUDQ2PSZrr",
                                              "VCVTUQQ2PDZ128rr",
                                              "VCVTUQQ2PDZ256rr",
-                                             "VCVTUQQ2PDZrr",
-                                             "VPLZCNTDZ128rr",
-                                             "VPLZCNTDZ256rr",
-                                             "VPLZCNTDZrr",
-                                             "VPLZCNTQZ128rr",
-                                             "VPLZCNTQZ256rr",
-                                             "VPLZCNTQZrr")>;
+                                             "VCVTUQQ2PDZrr")>;
 
 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
   let Latency = 4;
@@ -2681,9 +2675,7 @@ def: InstRW<[SKXWriteResGroup149], (inst
                                               "VCVTUDQ2PDZ128rm(b?)",
                                               "VCVTUDQ2PSZ128rm(b?)",
                                               "VCVTUQQ2PDZ128rm(b?)",
-                                              "VCVTUQQ2PSZ128rm(b?)",
-                                              "VPLZCNTDZ128rm(b?)",
-                                              "VPLZCNTQZ128rm(b?)")>;
+                                              "VCVTUQQ2PSZ128rm(b?)")>;
 
 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 10;
@@ -2807,11 +2799,7 @@ def: InstRW<[SKXWriteResGroup161], (inst
                                               "VCVTUDQ2PSZrm(b?)",
                                               "VCVTUQQ2PDZ256rm(b?)",
                                               "VCVTUQQ2PDZrm(b?)",
-                                              "VCVTUQQ2PSZ256rm(b?)",
-                                              "VPLZCNTDZ256rm(b?)",
-                                              "VPLZCNTDZrm(b?)",
-                                              "VPLZCNTQZ256rm(b?)",
-                                              "VPLZCNTQZrm(b?)")>;
+                                              "VCVTUQQ2PSZ256rm(b?)")>;
 
 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 11;