[PATCH] D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.

[Evandro Menezes via Phabricator via llvm-commits]

evandro added inline comments.


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:307
                                                     let NumMicroOps = 1;
-                                                    let ResourceCycles = [8]; }
+                                                    let ResourceCycles = [8, 1]; }
 def M3WriteNEONW   : SchedWriteRes<[M3UnitFDIV,
----------------
courbet wrote:
> evandro wrote:
> > Please, make this [8, 8]...
> Note that the two following definitions are strictly equivalent:
> 
> ```
> def M3WriteNEONV   : SchedWriteRes<[M3UnitFDIV, M3UnitFDIV]>  {
>   let Latency = 7;
>   let NumMicroOps = 1;
>   let ResourceCycles = [8,8];
> }
> ```
> 
> ```
> def M3WriteNEONV   : SchedWriteRes<[M3UnitFDIV]>  {
>   let Latency = 7;
>   let NumMicroOps = 1;
>   let ResourceCycles = [16];
> }
> ```
> 
> What's the semantics that you're trying to express by splitting into  `8*M3UnitFDIV + 8*M3UnitFDIV` vs `16*M3UnitFDIV` ? The SubtargetEmitter is destroying these semantics anyway.
> 
> For reference before this change the definition is equivalent to:
> 
> ```
> def M3WriteNEONV   : SchedWriteRes<[M3UnitFDIV]>  {
>   let Latency = 7;
>   let NumMicroOps = 1;
>   let ResourceCycles = [9];
> }
> ```
> 
> 
> 
There are two FDIV units in M3:

def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0, M3UnitFDIV1]>;



Repository:
  rL LLVM

https://reviews.llvm.org/D46356