[PATCH] D46333: [Power9]Legalize and emit code for DW vector extract and convert to Quad-Precision

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

If the definition of the new instruction can be avoided, feel free to do so on the commit. If it can't, add a comment as to why it is necessary in the code.
Other than that, LGTM.



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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:3163
+    def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
+              (f128 (XSCVSDQP (XXPERMDIq $src, 3)))>;
+    def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
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I am curious why we need another `CodeGenOnly` instruction here. It seems that for the version that doesn't require the splat, you can just accomplish what is necessary with a `COPY_TO_REGCLASS`. Why can't the output pattern here be something like:
`(f128 (XSCVSDQP (COPY_TO_REGCLASS (XXPERMDI $src, $src, 3), VFRC)))`


https://reviews.llvm.org/D46333