[PATCH] D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.

[Evandro Menezes via Phabricator via llvm-commits]

evandro added inline comments.


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:307
                                                     let NumMicroOps = 1;
-                                                    let ResourceCycles = [8]; }
+                                                    let ResourceCycles = [8, 1]; }
 def M3WriteNEONW   : SchedWriteRes<[M3UnitFDIV,
----------------
Please, make this [8, 8]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:311
                                                     let NumMicroOps = 1;
-                                                    let ResourceCycles = [13]; }
+                                                    let ResourceCycles = [13, 1]; }
 def M3WriteNEONX   : SchedWriteRes<[M3UnitFSQR,
----------------
[13, 13]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:315
                                                     let NumMicroOps = 1;
-                                                    let ResourceCycles = [19]; }
+                                                    let ResourceCycles = [19, 1]; }
 def M3WriteNEONY   : SchedWriteRes<[M3UnitFSQR,
----------------
[19, 19]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:319
                                                     let NumMicroOps = 1;
-                                                    let ResourceCycles = [26]; }
+                                                    let ResourceCycles = [26, 1]; }
 def M3WriteNEONZ   : SchedWriteRes<[M3UnitNMSC,
----------------
[26, 26]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:391
                                                     let NumMicroOps = 3;
-                                                    let ResourceCycles = [6]; }
+                                                    let ResourceCycles = [6, 1, 1]; }
 def M3WriteVLDJ    : SchedWriteRes<[M3UnitL,
----------------
[6, 6, 6]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:411
                                                     let NumMicroOps = 5;
-                                                    let ResourceCycles = [3]; }
+                                                    let ResourceCycles = [3, 1, 1, 1, 1]; }
 def M3WriteVLDM    : SchedWriteRes<[M3UnitL,
----------------
[6, 1, 1, 6, 1]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:419
                                                     let NumMicroOps = 6;
-                                                    let ResourceCycles = [3]; }
+                                                    let ResourceCycles = [3, 1, 1, 1, 1, 1]; }
 def M3WriteVLDN    : SchedWriteRes<[M3UnitL,
----------------
[6, 1, 1, 6, 1, 1]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:425
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [7]; }
+                                                    let ResourceCycles = [7, 1, 1, 1]; }
 def M3WriteVSTA    : WriteSequence<[WriteVST], 2>;
----------------
[6, 6, 6, 6]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:434
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [7]; }
+                                                    let ResourceCycles = [7, 1, 1, 1]; }
 def M3WriteVSTE    : SchedWriteRes<[M3UnitS,
----------------
[1, 3, 1, 3]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:442
                                                     let NumMicroOps = 3;
-                                                    let ResourceCycles = [8]; }
+                                                    let ResourceCycles = [8, 1, 1, 1, 1, 1]; }
 def M3WriteVSTF    : SchedWriteRes<[M3UnitNALU,
----------------
[1, 3, 1, 3, 1, 3]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:451
                                                     let NumMicroOps = 5;
-                                                    let ResourceCycles = [15]; }
+                                                    let ResourceCycles = [15, 1, 1, 1, 1, 1, 1]; }
 def M3WriteVSTG    : SchedWriteRes<[M3UnitNALU,
----------------
[1, 3, 3, 1, 3, 1, 3]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:462
                                                     let NumMicroOps = 6;
-                                                    let ResourceCycles = [16]; }
+                                                    let ResourceCycles = [16, 1, 1, 1, 1, 1, 1, 1, 1]; }
 def M3WriteVSTH    : SchedWriteRes<[M3UnitNALU,
----------------
[1, 3, 3, 1, 3, 1, 3, 1, 3]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:469
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [14]; }
+                                                    let ResourceCycles = [14, 1, 1, 1, 1]; }
 def M3WriteVSTI    : SchedWriteRes<[M3UnitNALU,
----------------
[1, 3, 3, 1, 3]...


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM3.td:480
                                                     let NumMicroOps = 7;
-                                                    let ResourceCycles = [17]; }
+                                                    let ResourceCycles = [17, 1, 1, 1, 1, 1, 1, 1, 1]; }
 
----------------
[1, 3, 3, 1, 3, 1, 3, 1, 3].


Repository:
  rL LLVM

https://reviews.llvm.org/D46356