[llvm] r331360 - [X86] Cleanup WriteFMul scheduler classes with more common default values
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed May 2 07:25:32 PDT 2018
Author: rksimon
Date: Wed May 2 07:25:32 2018
New Revision: 331360
URL: http://llvm.org/viewvc/llvm-project?rev=331360&view=rev
Log:
[X86] Cleanup WriteFMul scheduler classes with more common default values
Intel models were targeting x87 instead of packed sse.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=331360&r1=331359&r2=331360&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Wed May 2 07:25:32 2018
@@ -160,8 +160,8 @@ defm : BWWriteResPair<WriteFAddY, [BWPo
defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare.
defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags.
-defm : BWWriteResPair<WriteFMul, [BWPort0], 5, [1], 1, 5>; // Floating point multiplication.
-defm : BWWriteResPair<WriteFMulY, [BWPort0], 5, [1], 1, 7>; // Floating point multiplication (YMM/ZMM).
+defm : BWWriteResPair<WriteFMul, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication.
+defm : BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
defm : BWWriteResPair<WriteFDiv, [BWPort0], 12, [1], 1, 5>; // 10-14 cycles. // Floating point division.
defm : BWWriteResPair<WriteFDivY, [BWPort0], 12, [1], 1, 7>; // 10-14 cycles. // Floating point division (YMM/ZMM).
defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15, [1], 1, 5>; // Floating point square root.
@@ -657,16 +657,6 @@ def: InstRW<[BWWriteResGroup28], (instre
"VPMOVZXWDYrr",
"VPMOVZXWQYrr")>;
-def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
- let Latency = 3;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[BWWriteResGroup29], (instregex "(V?)MULPD(Y?)rr",
- "(V?)MULPS(Y?)rr",
- "(V?)MULSDrr",
- "(V?)MULSSrr")>;
-
def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
@@ -836,7 +826,10 @@ def BWWriteResGroup47 : SchedWriteRes<[B
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup47], (instregex "(V?)PCMPGTQ(Y?)rr")>;
+def: InstRW<[BWWriteResGroup47], (instregex "(V?)PCMPGTQ(Y?)rr",
+ "MUL_FPrST0",
+ "MUL_FST0r",
+ "MUL_FrST0")>;
def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
let Latency = 5;
@@ -1293,16 +1286,6 @@ def: InstRW<[BWWriteResGroup92], (instre
"VPMOVSXWQYrm",
"VPMOVZXWDYrm")>;
-def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
- let Latency = 8;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[BWWriteResGroup93], (instregex "(V?)MULPDrm",
- "(V?)MULPSrm",
- "(V?)MULSDrm",
- "(V?)MULSSrm")>;
-
def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
let Latency = 8;
let NumMicroOps = 3;
@@ -1389,14 +1372,6 @@ def: InstRW<[BWWriteResGroup102], (instr
"VPMOVZXDQYrm",
"VPMOVZXWQYrm")>;
-def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
- let Latency = 9;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
- "VMULPSYrm")>;
-
def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
let Latency = 9;
let NumMicroOps = 3;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=331360&r1=331359&r2=331360&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Wed May 2 07:25:32 2018
@@ -153,8 +153,8 @@ defm : HWWriteResPair<WriteFAddY, [HWPo
defm : HWWriteResPair<WriteFCmp, [HWPort1], 3, [1], 1, 6>;
defm : HWWriteResPair<WriteFCmpY, [HWPort1], 3, [1], 1, 7>;
defm : HWWriteResPair<WriteFCom, [HWPort1], 3>;
-defm : HWWriteResPair<WriteFMul, [HWPort0], 5, [1], 1, 5>;
-defm : HWWriteResPair<WriteFMulY, [HWPort0], 5, [1], 1, 7>;
+defm : HWWriteResPair<WriteFMul, [HWPort01], 5, [1], 1, 6>;
+defm : HWWriteResPair<WriteFMulY, [HWPort01], 5, [1], 1, 7>;
defm : HWWriteResPair<WriteFDiv, [HWPort0], 12, [1], 1, 5>; // 10-14 cycles.
defm : HWWriteResPair<WriteFDivY, [HWPort0], 12, [1], 1, 7>; // 10-14 cycles.
defm : HWWriteResPair<WriteFRcp, [HWPort0], 5, [1], 1, 5>;
@@ -1797,17 +1797,10 @@ def HWWriteResGroup89 : SchedWriteRes<[H
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup89], (instregex "(V?)PCMPGTQ(Y?)rr")>;
-
-def HWWriteResGroup90 : SchedWriteRes<[HWPort01]> {
- let Latency = 5;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[HWWriteResGroup90], (instregex "(V?)MULPD(Y?)rr",
- "(V?)MULPS(Y?)rr",
- "(V?)MULSDrr",
- "(V?)MULSSrr")>;
+def: InstRW<[HWWriteResGroup89], (instregex "(V?)PCMPGTQ(Y?)rr",
+ "MUL_FPrST0",
+ "MUL_FST0r",
+ "MUL_FrST0")>;
def HWWriteResGroup91_1 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 16;
@@ -1858,22 +1851,6 @@ def: InstRW<[HWWriteResGroup91_3], (inst
"VPMULUDQYrm",
"VPSADBWYrm")>;
-def HWWriteResGroup92 : SchedWriteRes<[HWPort01,HWPort23]> {
- let Latency = 11;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[HWWriteResGroup92], (instregex "(V?)MULPDrm",
- "(V?)MULPSrm")>;
-
-def HWWriteResGroup92_1 : SchedWriteRes<[HWPort01,HWPort23]> {
- let Latency = 12;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[HWWriteResGroup92_1], (instregex "VMULPDYrm",
- "VMULPSYrm")>;
-
def HWWriteResGroup92_2 : SchedWriteRes<[HWPort01,HWPort23]> {
let Latency = 10;
let NumMicroOps = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=331360&r1=331359&r2=331360&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Wed May 2 07:25:32 2018
@@ -156,8 +156,8 @@ defm : SKLWriteResPair<WriteFAddY, [SKLP
defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 6>; // Floating point compare.
defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>; // Floating point compare (YMM/ZMM).
defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags.
-defm : SKLWriteResPair<WriteFMul, [SKLPort0], 5, [1], 1, 5>; // Floating point multiplication.
-defm : SKLWriteResPair<WriteFMulY, [SKLPort0], 5, [1], 1, 7>; // Floating point multiplication (YMM/ZMM).
+defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 6>; // Floating point multiplication.
+defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>; // Floating point multiplication (YMM/ZMM).
defm : SKLWriteResPair<WriteFDiv, [SKLPort0], 12, [1], 1, 5>; // 10-14 cycles. // Floating point division.
defm : SKLWriteResPair<WriteFDivY, [SKLPort0], 12, [1], 1, 7>; // 10-14 cycles. // Floating point division (YMM/ZMM).
defm : SKLWriteResPair<WriteFSqrt, [SKLPort0], 15, [1], 1, 5>; // Floating point square root.
@@ -914,10 +914,6 @@ def SKLWriteResGroup48 : SchedWriteRes<[
def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr",
"(V?)CVTTPS2DQ(Y?)rr",
- "(V?)MULPD(Y?)rr",
- "(V?)MULPS(Y?)rr",
- "(V?)MULSDrr",
- "(V?)MULSSrr",
"(V?)PMADDUBSW(Y?)rr",
"(V?)PMADDWD(Y?)rr",
"(V?)PMULDQ(Y?)rr",
@@ -1818,8 +1814,6 @@ def: InstRW<[SKLWriteResGroup134], (inst
"(V?)CVTPS2DQrm",
"(V?)CVTSS2SDrm",
"(V?)CVTTPS2DQrm",
- "(V?)MULPDrm",
- "(V?)MULPSrm",
"(V?)PMADDUBSWrm",
"(V?)PMADDWDrm",
"(V?)PMULDQrm",
@@ -1916,8 +1910,6 @@ def: InstRW<[SKLWriteResGroup147], (inst
"VCVTPS2DQYrm",
"VCVTPS2PDYrm",
"VCVTTPS2DQYrm",
- "VMULPDYrm",
- "VMULPSYrm",
"VPMADDUBSWYrm",
"VPMADDWDYrm",
"VPMULDQYrm",
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