[llvm] r331348 - Revert "[mips] Correct the predicates of sign extension instructions"
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Wed May 2 05:35:29 PDT 2018
Author: sdardis
Date: Wed May 2 05:35:29 2018
New Revision: 331348
URL: http://llvm.org/viewvc/llvm-project?rev=331348&view=rev
Log:
Revert "[mips] Correct the predicates of sign extension instructions"
I accidently committed this patch after asking for a review, but it has not
been reviewed yet.
This reverts r331346.
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/micromips/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r3/valid.s
llvm/trunk/test/MC/Mips/mips32r5/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r3/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Wed May 2 05:35:29 2018
@@ -203,6 +203,20 @@ class LBU32_FM_MMR6 : MipsR6Inst {
let Inst{15-0} = offset;
}
+class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
+ : MMR6Arch<instr_asm> {
+ bits<5> rd;
+ bits<5> rt;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0b000000;
+ let Inst{25-21} = rd;
+ let Inst{20-16} = rt;
+ let Inst{15-6} = funct;
+ let Inst{5-0} = 0b111100;
+}
+
class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
bits<5> rt;
bits<19> imm;
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed May 2 05:35:29 2018
@@ -136,6 +136,8 @@ class OR_MMR6_ENC : ARITH_FM_MMR6<"or",
class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
+class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
+class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
@@ -527,6 +529,8 @@ class AUI_MMR6_DESC_BASE<string instr_as
class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
+class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
+class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
InstrItinClass Itin> : MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt);
@@ -1378,6 +1382,8 @@ def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC,
def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
+def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
+def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
ISA_MICROMIPS32R6;
def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
@@ -1654,6 +1660,10 @@ def : MipsInstAlias<"xor $rs, $imm",
def : MipsInstAlias<"not $rt, $rs",
(NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
ISA_MICROMIPS32R6;
+def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
+ ISA_MICROMIPS32R6;
+def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
+ ISA_MICROMIPS32R6;
def : MipsInstAlias<"lapc $rd, $imm",
(ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
ISA_MICROMIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Wed May 2 05:35:29 2018
@@ -927,9 +927,9 @@ let DecoderNamespace = "MicroMips", Pred
/// Sign Ext In Register Instructions.
def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
- SEB_FM_MM<0x0ac>, ISA_MICROMIPS;
+ SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
- SEB_FM_MM<0x0ec>, ISA_MICROMIPS;
+ SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
/// Word Swap Bytes Within Halfwords
def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
@@ -1325,9 +1325,9 @@ let Predicates = [InMicroMips] in {
(BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
ISA_MICROMIPS;
def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
- ISA_MICROMIPS;
+ ISA_MIPS32R2_NOT_32R6_64R6;
def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
- ISA_MICROMIPS;
+ ISA_MIPS32R2_NOT_32R6_64R6;
def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>,
ISA_MICROMIPS;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed May 2 05:35:29 2018
@@ -2285,13 +2285,13 @@ def MFHI : MMRel, MoveFromLOHI<"mfhi", G
ISA_MIPS1_NOT_32R6_64R6;
def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
ISA_MIPS1_NOT_32R6_64R6;
+}
/// Sign Ext In Register Instructions.
def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
-}
/// Count Leading
def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>,
Modified: llvm/trunk/test/MC/Mips/micromips/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/valid.s?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/valid.s Wed May 2 05:35:29 2018
@@ -150,13 +150,9 @@ neg.d $f0, $f2 # CHECK: neg
clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c]
clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c]
seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c]
- # CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM
seb $9 # CHECK: seb $9, $9 # encoding: [0x01,0x29,0x2b,0x3c]
- # CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM
seh $9, $6 # CHECK: seh $9, $6 # encoding: [0x01,0x26,0x3b,0x3c]
- # CHECK-NEXT: # <MCInst #{{[0-9]+}} SEH_MM
seh $9 # CHECK: seh $9, $9 # encoding: [0x01,0x29,0x3b,0x3c]
- # CHECK-NEXT: # <MCInst #{{[0-9]+}} SEH_MM
wsbh $9, $6 # CHECK: wsbh $9, $6 # encoding: [0x01,0x26,0x7b,0x3c]
ext $9, $6, 3, 7 # CHECK: ext $9, $6, 3, 7 # encoding: [0x01,0x26,0x30,0xec]
ins $9, $6, 3, 7 # CHECK: ins $9, $6, 3, 7 # encoding: [0x01,0x26,0x48,0xcc]
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Wed May 2 05:35:29 2018
@@ -235,13 +235,9 @@ a:
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid.s?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid.s Wed May 2 05:35:29 2018
@@ -235,13 +235,9 @@ a:
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid.s?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s Wed May 2 05:35:29 2018
@@ -236,13 +236,9 @@ a:
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Wed May 2 05:35:29 2018
@@ -201,13 +201,9 @@ a:
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Wed May 2 05:35:29 2018
@@ -305,13 +305,9 @@ a:
sdr $11,-20423($12)
sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid.s?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s Wed May 2 05:35:29 2018
@@ -299,13 +299,9 @@ a:
sdr $11,-20423($12)
sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Wed May 2 05:35:29 2018
@@ -300,13 +300,9 @@ a:
sdr $11,-20423($12)
sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=331348&r1=331347&r2=331348&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Wed May 2 05:35:29 2018
@@ -239,14 +239,10 @@ a:
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17]
- seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
- seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
- seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
- seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
- # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
+ seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
+ seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
+ seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
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