[PATCH] D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.

[Clement Courbet via Phabricator via llvm-commits]

courbet created this revision.
courbet added reviewers: RKSimon, craig.topper.
Herald added a reviewer: javed.absar.
Herald added a subscriber: kristof.beyls.

For targets I'm not familiar with, I've automatically made the "default to 1 for each resource" behaviour explicit in the td files.
For more obvious cases, I've ventured a fix.

Some notes:

- Exynos is especially fishy.
- AArch64SchedThunderX2T99.td had some truncated entries. If I understand correctly, the person who wrote that interpreted the ResourceCycle as a range. I made the decision to use the upper/lower bound for consistency with the 'Latency' value. I'm sure there is a better choice.
- The change to X86ScheduleBtVer2.td is an NFC, it just makes values more explicit.

Also see PR37310.


Repository:
  rL LLVM

https://reviews.llvm.org/D46356

Files:
  lib/Target/AArch64/AArch64SchedExynosM1.td
  lib/Target/AArch64/AArch64SchedExynosM3.td
  lib/Target/AArch64/AArch64SchedThunderX2T99.td
  lib/Target/ARM/ARMScheduleA9.td
  lib/Target/X86/X86SchedBroadwell.td
  lib/Target/X86/X86ScheduleBtVer2.td
  lib/Target/X86/X86ScheduleSLM.td
  lib/Target/X86/X86ScheduleZnver1.td
  utils/TableGen/SubtargetEmitter.cpp

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