[PATCH] D44830: Introduce codegen for the Signal Processing Engine

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

Thank you so much for your patience with this long review cycle. Aside from a few minor nits, LGTM.
I also imagine you'll need something for the https://reviews.llvm.org/P9 scheduler since we've now marked the model as complete. Probably something along the lines of:

  Index: lib/Target/PowerPC/PPCScheduleP9.td
  ===================================================================
  --- lib/Target/PowerPC/PPCScheduleP9.td (revision 331260)
  +++ lib/Target/PowerPC/PPCScheduleP9.td (working copy)
  @@ -35,8 +35,9 @@
   
     let CompleteModel = 1;
   
  -  // Do not support QPX (Quad Processing eXtension) on Power 9.
  -  let UnsupportedFeatures = [HasQPX];
  +  // Do not support QPX (Quad Processing eXtension) or SPE (Signal Processing
  +  // Engine) on Power 9.
  +  let UnsupportedFeatures = [HasQPX, HasSPE];
   
   }
   



================
Comment at: lib/Target/PowerPC/PPCAsmPrinter.cpp:516
+  if (!MI->isInlineAsm()) {
+    for (unsigned i = 0; i < MI->getNumOperands(); i++) {
+      const MachineOperand &MO = MI->getOperand(i);
----------------
I think this can be a range-based for loop over `MI->operands()`.


================
Comment at: lib/Target/PowerPC/PPCCallingConv.td:271
 
-def CSR_SVR432   : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
-                                        R21, R22, R23, R24, R25, R26, R27, R28,
-                                        R29, R30, R31, F14, F15, F16, F17, F18,
+// SPE does not use FPRs, so break out the common register set as base
+def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
----------------
Nit: full sentence comments with a period.


Repository:
  rL LLVM

https://reviews.llvm.org/D44830