[PATCH] D45990: GlobalISel/InstructionSelector: Implement GIR_CopyFConstantAsFPImm

[Tom Stellard via Phabricator via llvm-commits]

tstellar added a comment.

In https://reviews.llvm.org/D45990#1084322, @dsanders wrote:

> In https://reviews.llvm.org/D45990#1084299, @tstellar wrote:
>
> > I actually don't have a test case of this.  I really just need the enum defined so AMDGPUGenGlobalIsel.inc will build.  I can drop the implementation and just add the enum value if you prefer.
>
>
> Could you send me the comment that's shortly before the GIR_CopyFConstantAsFPImm in AMDGPUGenGlobalIsel.inc? It should look similar to a tablegen pattern and we can probably derive a test case from that. I'm not sure which rule has been imported but I'm hoping it will be something like (set $rd:GPR, $imm:fpimm) in which case the test would be similar to test/CodeGen/AArch64/GlobalISel/select-constant.mir.


Here is the comment.  Note that the reason I don't have a test case is because this pattern is only for the R600 sub-target and I'm not implementing global-isel for that sub-target:

  // MIs[0] Operand 1
  // No operand predicates
  // (fpimm:{ *:[f32] }):$val  =>  (MOV_IMM_F32:{ *:[f32] } (fpimm:{ *:[f32] }):$val)
  GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::MOV_IMM_F32,
  GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
  GIR_CopyFConstantAsFPImm, /*NewInsnID*/0, /*OldInsnID*/0, // va


Repository:
  rL LLVM

https://reviews.llvm.org/D45990