[PATCH] D46311: [AArch64] added FP16 vcvth intrinsic support

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll:131-200
+define dso_local half @test_vcvth_n_f16_s16(i16 %a) local_unnamed_addr #0 {
+entry:
+  %sext = sext i16 %a to i32
+  %fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %sext, i32 1)
+  ret half %fcvth_n
+}
+
----------------
Is it intentional that there are no `; CHECK` lines?


Repository:
  rL LLVM

https://reviews.llvm.org/D46311