[llvm] r331260 - [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Tue May 1 06:36:03 PDT 2018
Author: s.desmalen
Date: Tue May 1 06:36:03 2018
New Revision: 331260
URL: http://llvm.org/viewvc/llvm-project?rev=331260&view=rev
Log:
[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46121
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st1b.s
llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st1d.s
llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st1h.s
llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st1w.s
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=331260&r1=331259&r2=331260&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Tue May 1 06:36:03 2018
@@ -230,6 +230,18 @@ let Predicates = [HasSVE] in {
defm ST1W_D_IMM : sve_mem_cst_si<0b10, 0b11, "st1w", Z_d, ZPR64>;
defm ST1D_IMM : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>;
+ // contiguous store with reg+reg addressing.
+ defm ST1B : sve_mem_cst_ss<0b0000, "st1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
+ defm ST1B_H : sve_mem_cst_ss<0b0001, "st1b", Z_h, ZPR16, GPR64NoXZRshifted8>;
+ defm ST1B_S : sve_mem_cst_ss<0b0010, "st1b", Z_s, ZPR32, GPR64NoXZRshifted8>;
+ defm ST1B_D : sve_mem_cst_ss<0b0011, "st1b", Z_d, ZPR64, GPR64NoXZRshifted8>;
+ defm ST1H : sve_mem_cst_ss<0b0101, "st1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
+ defm ST1H_S : sve_mem_cst_ss<0b0110, "st1h", Z_s, ZPR32, GPR64NoXZRshifted16>;
+ defm ST1H_D : sve_mem_cst_ss<0b0111, "st1h", Z_d, ZPR64, GPR64NoXZRshifted16>;
+ defm ST1W : sve_mem_cst_ss<0b1010, "st1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
+ defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
+ defm ST1D : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
+
// ST{2,3,4}{B,H,W,D} with immediate
defm ST2B_IMM : sve_mem_est_si<0b00, 0b01, ZZ_b, "st2b", simm4s2>;
defm ST3B_IMM : sve_mem_est_si<0b00, 0b10, ZZZ_b, "st3b", simm4s3>;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=331260&r1=331259&r2=331260&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Tue May 1 06:36:03 2018
@@ -560,6 +560,36 @@ multiclass sve_mem_est_si<bits<2> sz, bi
(!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
}
+class sve_mem_cst_ss_base<bits<4> dtype, string asm,
+ RegisterOperand listty, RegisterOperand gprty>
+: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+ asm, "\t$Zt, $Pg, [$Rn, $Rm]",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Rm;
+ bits<5> Rn;
+ bits<5> Zt;
+ let Inst{31-25} = 0b1110010;
+ let Inst{24-21} = dtype;
+ let Inst{20-16} = Rm;
+ let Inst{15-13} = 0b010;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayStore = 1;
+}
+
+multiclass sve_mem_cst_ss<bits<4> dtype, string asm,
+ RegisterOperand listty, ZPRRegOp zprty,
+ RegisterOperand gprty> {
+ def NAME : sve_mem_cst_ss_base<dtype, asm, listty, gprty>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
+ (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+}
+
//===----------------------------------------------------------------------===//
// SVE Permute - Predicates Group
//===----------------------------------------------------------------------===//
@@ -916,4 +946,4 @@ multiclass sve_mem_64b_gld_vi_64_ptrs<bi
(!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
(!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
-}
\ No newline at end of file
+}
Modified: llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s?rev=331260&r1=331259&r2=331260&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s Tue May 1 06:36:03 2018
@@ -83,3 +83,27 @@ st1b { v0.16b }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st1b { v0.16b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1b z0.b, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b z0.b, p0, [x0, x0, lsl #1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, x0, lsl #1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b z0.b, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b z0.b, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/st1b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1b.s?rev=331260&r1=331259&r2=331260&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1b.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1b.s Tue May 1 06:36:03 2018
@@ -102,3 +102,27 @@ st1b { z21.d }, p5, [x10, #5, mul vl]
// CHECK-ENCODING: [0x55,0xf5,0x65,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 f5 65 e4 <unknown>
+
+st1b { z0.b }, p0, [x0, x0]
+// CHECK-INST: st1b { z0.b }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x00,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 e4 <unknown>
+
+st1b { z0.h }, p0, [x0, x0]
+// CHECK-INST: st1b { z0.h }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x20,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 20 e4 <unknown>
+
+st1b { z0.s }, p0, [x0, x0]
+// CHECK-INST: st1b { z0.s }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x40,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 e4 <unknown>
+
+st1b { z0.d }, p0, [x0, x0]
+// CHECK-INST: st1b { z0.d }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x60,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 60 e4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s?rev=331260&r1=331259&r2=331260&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s Tue May 1 06:36:03 2018
@@ -39,3 +39,32 @@ st1d { v0.2d }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st1d { v0.2d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1d z0.d, p0, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/st1d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1d.s?rev=331260&r1=331259&r2=331260&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1d.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1d.s Tue May 1 06:36:03 2018
@@ -30,3 +30,9 @@ st1d { z21.d }, p5, [x10, #5, mul vl]
// CHECK-ENCODING: [0x55,0xf5,0xe5,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 f5 e5 e5 <unknown>
+
+st1d { z0.d }, p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d { z0.d }, p0, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x40,0xe0,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 e0 e5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s?rev=331260&r1=331259&r2=331260&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s Tue May 1 06:36:03 2018
@@ -68,3 +68,32 @@ st1h { v0.8h }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st1h { v0.8h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1h z0.h, p0, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/st1h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1h.s?rev=331260&r1=331259&r2=331260&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1h.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1h.s Tue May 1 06:36:03 2018
@@ -78,3 +78,21 @@ st1h { z31.d }, p7, [sp, #-1, mul vl]
// CHECK-ENCODING: [0xff,0xff,0xef,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff ef e4 <unknown>
+
+st1h { z0.h }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h { z0.h }, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x40,0xa0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 a0 e4 <unknown>
+
+st1h { z0.s }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h { z0.s }, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x40,0xc0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 e4 <unknown>
+
+st1h { z0.d }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h { z0.d }, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x40,0xe0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 e0 e4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s?rev=331260&r1=331259&r2=331260&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s Tue May 1 06:36:03 2018
@@ -56,3 +56,32 @@ st1w { v0.4s }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st1w { v0.4s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1w z0.s, p0, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/st1w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1w.s?rev=331260&r1=331259&r2=331260&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1w.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1w.s Tue May 1 06:36:03 2018
@@ -54,3 +54,15 @@ st1w { z21.d }, p5, [x10, #5, mul vl]
// CHECK-ENCODING: [0x55,0xf5,0x65,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 f5 65 e5 <unknown>
+
+st1w { z0.s }, p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w { z0.s }, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x40,0x40,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 e5 <unknown>
+
+st1w { z0.d }, p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w { z0.d }, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x40,0x60,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 60 e5 <unknown>
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