[PATCH] D46310: [AArch64] Disallow vector operand if FPR128 Q register is required.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: aemerson, Gerolf, SjoerdMeijer.
Herald added subscribers: kristof.beyls, rengolin.
Herald added a reviewer: javed.absar.

Patch https://reviews.llvm.org/D41445 changed the behaviour of 'isReg()'
to also return 'true' if the parsed register operand is a vector
register. Code in the AsmMatcher checks if a register is a subclass of the
expected register class. However, even though both parsed registers map
to the same physical register, the 'v' register is of kind 'NeonVector',
where 'q' is of type Scalar, where isSubclass() does not distinguish
between the two cases.

The solution is to use an AsmOperand instead of the register directly,
and use the PredicateMethod to distinguish the two operands.

This fixes for example:

  ldr v0, [x0]    // 'v0' is an invalid operand for this instruction
  ldr q0, [x0]    // valid


https://reviews.llvm.org/D46310

Files:
  lib/Target/AArch64/AArch64InstrFormats.td
  lib/Target/AArch64/AArch64InstrInfo.td
  lib/Target/AArch64/AArch64RegisterInfo.td
  test/MC/AArch64/basic-a64-diagnostics.s

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