[PATCH] D46009: [AArch64] Custom Lower MULLH{S, U} for v16i8, v8i16, and v4i32

[Adhemerval Zanella via Phabricator via llvm-commits]

zatrazz added inline comments.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:2557
 
+static SDValue LowerMULH(SDValue Op, SelectionDAG &DAG, bool sign) {
+  EVT VT = Op.getValueType();
----------------
SjoerdMeijer wrote:
> Do you need to pass the 'sign' boolean? Can you not look at the opcode and check for ISD::MULHS or ISD::MULHU?
Yes, you can divise the correct ISD from SDValue opcode, I will change it.


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Comment at: test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll:3
+
+define <16 x i8> @mul8xi16(<16 x i8> %x) {
+; CHECK-LABEL: mul8xi16:
----------------
SjoerdMeijer wrote:
> nit: this is mul16xi8
Ack.


================
Comment at: test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll:14
+
+define <8 x i16> @mul16xi8(<8 x i16> %x) {
+; CHECK-LABEL: mul16xi8:
----------------
SjoerdMeijer wrote:
> nit: this is mul8xi16
Ack.


Repository:
  rL LLVM

https://reviews.llvm.org/D46009