[PATCH] D45395: [RISCV] Implement tail call optimization

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

Thanks Mandeep. I'll re-review properly once this is rebased against https://reviews.llvm.org/D46221.



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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:1309-1314
+      } else {
+        MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
+        int FI = MFI.CreateFixedObject(ArgValue.getValueSizeInBits() / 8,
+                                       VA.getLocMemOffset(), false);
+        SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
+        return DAG.getStore(Chain, DL, ArgValue, FIN, MachinePointerInfo(),
----------------
Isn't this code dead now that tail calls are never used when parameters are passed on the stack?


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Comment at: lib/Target/RISCV/RISCVRegisterInfo.td:134
+def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add
+    (sequence "X%u", 5, 7)
+  )> {
----------------
HsiangKai wrote:
> mgrang wrote:
> > Can we also use x28-x31 (Caller temporaries) here?
> Could we also use x10-x17 (Argument registers)?
> 
> I think we could let RA use any registers except callee-saved registers and x0-x4.
> 
> We could not use callee-saved registers, because these registers will be restored before tailcall and the address register will be clobbered.
> We could not use x0-x4, because these registers have special meaning in RISCV architecture.
I agree with @HsiangKai, it seems as though any register that isn't callee-saved (or otherwise has a special meaning) should be safe to use. Or at least, all such registers will avoid the problem described in the comment.


https://reviews.llvm.org/D45395