[PATCH] D46121: [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Are you referring to the 'assembler syntax' table? I think this table needs to be read in conjunction with the following paragraph (section 5.2.2, page 42):

> Load, store, and prefetch instructions that multiply a scalar index register or an index vector element by the memory element access size specify a shift type, followed by a shift amount in bits. The shift type can be one of LSL, SXTW, or UXTW. The shift amount is always Log2 of the memory element access size, in bytes. The shift amount defaults to zero when the memory element access size is a byte. The shift type of LSL must be omitted if the shift amount is omitted.


https://reviews.llvm.org/D46121