[llvm] r331145 - [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 29 10:33:38 PDT 2018
Author: s.desmalen
Date: Sun Apr 29 10:33:38 2018
New Revision: 331145
URL: http://llvm.org/viewvc/llvm-project?rev=331145&view=rev
Log:
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46120
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1b.s
llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1d.s
llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1h.s
llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1sb.s
llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1sh.s
llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1sw.s
llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1w.s
llvm/trunk/test/MC/AArch64/SVE/ldff1b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1b.s
llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1d.s
llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1h.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sb.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sh.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sw.s
llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1w.s
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Sun Apr 29 10:33:38 2018
@@ -196,6 +196,13 @@ def SImm10s8Operand : AsmOperandClass {
let PredicateMethod = "isSImmScaled<10, 8>";
}
+class UImmScaledMemoryIndexed<int Width, int Scale> : AsmOperandClass {
+ let Name = "UImm" # Width # "s" # Scale;
+ let DiagnosticType = "InvalidMemoryIndexed" # Scale # "UImm" # Width;
+ let RenderMethod = "addImmScaledOperands<" # Scale # ">";
+ let PredicateMethod = "isUImmScaled<" # Width # ", " # Scale # ">";
+}
+
//===----------------------------------------------------------------------===//
// Operand Definitions.
//
@@ -291,6 +298,28 @@ def am_indexed7s32 : ComplexPattern<i64
def am_indexed7s64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S64", []>;
def am_indexed7s128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S128", []>;
+// uimm5sN predicate - True if the immediate is a multiple of N in the range
+// [0 * N, 32 * N].
+def UImm5s2Operand : UImmScaledMemoryIndexed<5, 2>;
+def UImm5s4Operand : UImmScaledMemoryIndexed<5, 4>;
+def UImm5s8Operand : UImmScaledMemoryIndexed<5, 8>;
+
+def uimm5s2 : Operand<i64>, ImmLeaf<i64,
+ [{ return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); }]> {
+ let ParserMatchClass = UImm5s2Operand;
+ let PrintMethod = "printImmScale<2>";
+}
+def uimm5s4 : Operand<i64>, ImmLeaf<i64,
+ [{ return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); }]> {
+ let ParserMatchClass = UImm5s4Operand;
+ let PrintMethod = "printImmScale<4>";
+}
+def uimm5s8 : Operand<i64>, ImmLeaf<i64,
+ [{ return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); }]> {
+ let ParserMatchClass = UImm5s8Operand;
+ let PrintMethod = "printImmScale<8>";
+}
+
class AsmImmRange<int Low, int High> : AsmOperandClass {
let Name = "Imm" # Low # "_" # High;
let DiagnosticType = "InvalidImm" # Low # "_" # High;
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Sun Apr 29 10:33:38 2018
@@ -128,6 +128,36 @@ let Predicates = [HasSVE] in {
defm GLD1W : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
+ // Gathers using scaled 32-bit pointers with offset, e.g.
+ // ld1h z0.s, p0/z, [z0.s, #16]
+ defm GLD1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0000, "ld1sb", imm0_31>;
+ defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31>;
+ defm GLD1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0010, "ld1b", imm0_31>;
+ defm GLDFF1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0011, "ldff1b", imm0_31>;
+ defm GLD1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh", uimm5s2>;
+ defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2>;
+ defm GLD1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0110, "ld1h", uimm5s2>;
+ defm GLDFF1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0111, "ldff1h", uimm5s2>;
+ defm GLD1W : sve_mem_32b_gld_vi_32_ptrs<0b1010, "ld1w", uimm5s4>;
+ defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4>;
+
+ // Gathers using scaled 64-bit pointers with offset, e.g.
+ // ld1h z0.d, p0/z, [z0.d, #16]
+ defm GLD1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0000, "ld1sb", imm0_31>;
+ defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31>;
+ defm GLD1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0010, "ld1b", imm0_31>;
+ defm GLDFF1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0011, "ldff1b", imm0_31>;
+ defm GLD1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh", uimm5s2>;
+ defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2>;
+ defm GLD1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0110, "ld1h", uimm5s2>;
+ defm GLDFF1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0111, "ldff1h", uimm5s2>;
+ defm GLD1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1000, "ld1sw", uimm5s4>;
+ defm GLDFF1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1001, "ldff1sw", uimm5s4>;
+ defm GLD1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1010, "ld1w", uimm5s4>;
+ defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4>;
+ defm GLD1D : sve_mem_64b_gld_vi_64_ptrs<0b1110, "ld1d", uimm5s8>;
+ defm GLDFF1D : sve_mem_64b_gld_vi_64_ptrs<0b1111, "ldff1d", uimm5s8>;
+
// Gathers using unscaled 64-bit offsets, e.g.
// ld1h z0.d, p0/z, [x0, z0.d]
defm GLD1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0000, "ld1sb">;
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Sun Apr 29 10:33:38 2018
@@ -506,8 +506,16 @@ public:
template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
+ template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
+ return isImmScaled<Bits, Scale>(true);
+ }
+
+ template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
+ return isImmScaled<Bits, Scale>(false);
+ }
+
template <int Bits, int Scale>
- DiagnosticPredicate isSImmScaled() const {
+ DiagnosticPredicate isImmScaled(bool Signed) const {
if (!isImm())
return DiagnosticPredicateTy::NoMatch;
@@ -515,9 +523,15 @@ public:
if (!MCE)
return DiagnosticPredicateTy::NoMatch;
- int64_t Shift = Bits - 1;
- int64_t MinVal = (int64_t(1) << Shift) * -Scale;
- int64_t MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
+ int64_t MinVal, MaxVal;
+ if (Signed) {
+ int64_t Shift = Bits - 1;
+ MinVal = (int64_t(1) << Shift) * -Scale;
+ MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
+ } else {
+ MinVal = 0;
+ MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
+ }
int64_t Val = MCE->getValue();
if (Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0)
@@ -3754,6 +3768,12 @@ bool AArch64AsmParser::showMatchError(SM
return Error(Loc, "index must be a multiple of 8 in range [-512, 504].");
case Match_InvalidMemoryIndexed16SImm7:
return Error(Loc, "index must be a multiple of 16 in range [-1024, 1008].");
+ case Match_InvalidMemoryIndexed8UImm5:
+ return Error(Loc, "index must be a multiple of 8 in range [0, 248].");
+ case Match_InvalidMemoryIndexed4UImm5:
+ return Error(Loc, "index must be a multiple of 4 in range [0, 124].");
+ case Match_InvalidMemoryIndexed2UImm5:
+ return Error(Loc, "index must be a multiple of 2 in range [0, 62].");
case Match_InvalidMemoryWExtend8:
return Error(Loc,
"expected 'uxtw' or 'sxtw' with optional shift of #0");
@@ -4313,6 +4333,9 @@ bool AArch64AsmParser::MatchAndEmitInstr
case Match_InvalidMemoryIndexed4SImm7:
case Match_InvalidMemoryIndexed8SImm7:
case Match_InvalidMemoryIndexed16SImm7:
+ case Match_InvalidMemoryIndexed8UImm5:
+ case Match_InvalidMemoryIndexed4UImm5:
+ case Match_InvalidMemoryIndexed2UImm5:
case Match_InvalidMemoryIndexedSImm6:
case Match_InvalidMemoryIndexedSImm5:
case Match_InvalidMemoryIndexedSImm9:
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Sun Apr 29 10:33:38 2018
@@ -818,6 +818,41 @@ multiclass sve_mem_32b_gld_vs_32_unscale
}
+class sve_mem_32b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
+: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
+ asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Zn;
+ bits<5> Zt;
+ bits<5> imm5;
+ let Inst{31-25} = 0b1000010;
+ let Inst{24-23} = opc{3-2};
+ let Inst{22-21} = 0b01;
+ let Inst{20-16} = imm5;
+ let Inst{15} = 0b1;
+ let Inst{14-13} = opc{1-0};
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
+ let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+ let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty> {
+ def _IMM_REAL : sve_mem_32b_gld_vi<opc, asm, imm_ty>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
+ (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>;
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
+ (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
+ (!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
+}
+
//===----------------------------------------------------------------------===//
// SVE Memory - 64-bit Gather Group
//===----------------------------------------------------------------------===//
@@ -889,3 +924,38 @@ multiclass sve_mem_64b_gld_vs2_64_unscal
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
(!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
}
+
+class sve_mem_64b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
+: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
+ asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Zn;
+ bits<5> Zt;
+ bits<5> imm5;
+ let Inst{31-25} = 0b1100010;
+ let Inst{24-23} = opc{3-2};
+ let Inst{22-21} = 0b01;
+ let Inst{20-16} = imm5;
+ let Inst{15} = 0b1;
+ let Inst{14-13} = opc{1-0};
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
+ let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+ let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> {
+ def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
+ (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
+ (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
+ (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
+}
\ No newline at end of file
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -153,3 +153,27 @@ ld1b z0.d, p0/z, [x0, z0.d, sxtw #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.d, sxtw #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1b z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1b z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z0.s, p0/z, [z0.s, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1b z0.s, p0/z, [z0.s, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1b z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z0.d, p0/z, [z0.d, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1b z0.d, p0/z, [z0.d, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1b.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1b.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1b.s Sun Apr 29 10:33:38 2018
@@ -168,3 +168,27 @@ ld1b { z21.d }, p5/z, [x10, z21.d, sx
// CHECK-ENCODING: [0x55,0x55,0x55,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 55 55 c4 <unknown>
+
+ld1b { z31.s }, p7/z, [z31.s, #31]
+// CHECK-INST: ld1b { z31.s }, p7/z, [z31.s, #31]
+// CHECK-ENCODING: [0xff,0xdf,0x3f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 3f 84 <unknown>
+
+ld1b { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ld1b { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 20 84 <unknown>
+
+ld1b { z31.d }, p7/z, [z31.d, #31]
+// CHECK-INST: ld1b { z31.d }, p7/z, [z31.d, #31]
+// CHECK-ENCODING: [0xff,0xdf,0x3f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 3f c4 <unknown>
+
+ld1b { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1b { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 20 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -93,3 +93,42 @@ ld1d z0.d, p0/z, [x0, z0.d, lsl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
// CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1d z0.s, p0/z, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1d z0.s, p0/z, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.s, p0/z, [z0.s, #8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1d z0.s, p0/z, [z0.s, #8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [z0.d, #-8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #-8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [z0.d, #249]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #249]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [z0.d, #256]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #256]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1d.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1d.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1d.s Sun Apr 29 10:33:38 2018
@@ -78,3 +78,15 @@ ld1d { z0.d }, p0/z, [x0, z0.d, sxtw
// CHECK-ENCODING: [0x00,0x40,0xe0,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 e0 c5 <unknown>
+
+ld1d { z31.d }, p7/z, [z31.d, #248]
+// CHECK-INST: ld1d { z31.d }, p7/z, [z31.d, #248]
+// CHECK-ENCODING: [0xff,0xdf,0xbf,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df bf c5 <unknown>
+
+ld1d { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1d { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xc0,0xa0,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 a0 c5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -138,3 +138,57 @@ ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1h z0.s, p0/z, [z0.s, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.s, p0/z, [z0.s, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.s, p0/z, [z0.s, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.d, p0/z, [z0.d, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.d, p0/z, [z0.d, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.d, p0/z, [z0.d, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1h.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1h.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1h.s Sun Apr 29 10:33:38 2018
@@ -162,3 +162,27 @@ ld1h { z0.d }, p0/z, [x0, z0.d, sxtw
// CHECK-ENCODING: [0x00,0x40,0xe0,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 e0 c4 <unknown>
+
+ld1h { z31.s }, p7/z, [z31.s, #62]
+// CHECK-INST: ld1h { z31.s }, p7/z, [z31.s, #62]
+// CHECK-ENCODING: [0xff,0xdf,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df bf 84 <unknown>
+
+ld1h { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ld1h { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xc0,0xa0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 a0 84 <unknown>
+
+ld1h { z31.d }, p7/z, [z31.d, #62]
+// CHECK-INST: ld1h { z31.d }, p7/z, [z31.d, #62]
+// CHECK-ENCODING: [0xff,0xdf,0xbf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df bf c4 <unknown>
+
+ld1h { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1h { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xc0,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 a0 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -151,3 +151,27 @@ ld1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1sb z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1sb z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z0.s, p0/z, [z0.s, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1sb z0.s, p0/z, [z0.s, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z0.d, p0/z, [z0.d, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1sb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sb.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sb.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sb.s Sun Apr 29 10:33:38 2018
@@ -138,3 +138,27 @@ ld1sb { z21.d }, p5/z, [x10, z21.d, sx
// CHECK-ENCODING: [0x55,0x15,0x55,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 15 55 c4 <unknown>
+
+ld1sb { z31.s }, p7/z, [z31.s, #31]
+// CHECK-INST: ld1sb { z31.s }, p7/z, [z31.s, #31]
+// CHECK-ENCODING: [0xff,0x9f,0x3f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 3f 84 <unknown>
+
+ld1sb { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ld1sb { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0x80,0x20,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 20 84 <unknown>
+
+ld1sb { z31.d }, p7/z, [z31.d, #31]
+// CHECK-INST: ld1sb { z31.d }, p7/z, [z31.d, #31]
+// CHECK-ENCODING: [0xff,0x9f,0x3f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 3f c4 <unknown>
+
+ld1sb { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1sb { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0x80,0x20,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 20 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -137,3 +137,57 @@ ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1sh z0.s, p0/z, [z0.s, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [z0.s, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [z0.s, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.d, p0/z, [z0.d, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.d, p0/z, [z0.d, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.d, p0/z, [z0.d, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1sh.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sh.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sh.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sh.s Sun Apr 29 10:33:38 2018
@@ -132,3 +132,27 @@ ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw
// CHECK-ENCODING: [0x00,0x00,0xe0,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 e0 c4 <unknown>
+
+ld1sh { z31.s }, p7/z, [z31.s, #62]
+// CHECK-INST: ld1sh { z31.s }, p7/z, [z31.s, #62]
+// CHECK-ENCODING: [0xff,0x9f,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f bf 84 <unknown>
+
+ld1sh { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ld1sh { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0x80,0xa0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 a0 84 <unknown>
+
+ld1sh { z31.d }, p7/z, [z31.d, #62]
+// CHECK-INST: ld1sh { z31.d }, p7/z, [z31.d, #62]
+// CHECK-ENCODING: [0xff,0x9f,0xbf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f bf c4 <unknown>
+
+ld1sh { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1sh { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0x80,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 a0 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -127,3 +127,42 @@ ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1sw z0.s, p0/z, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.s, p0/z, [z0.s, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [z0.d, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [z0.d, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [z0.d, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1sw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sw.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sw.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sw.s Sun Apr 29 10:33:38 2018
@@ -78,3 +78,15 @@ ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw
// CHECK-ENCODING: [0x00,0x00,0x60,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 60 c5 <unknown>
+
+ld1sw { z31.d }, p7/z, [z31.d, #124]
+// CHECK-INST: ld1sw { z31.d }, p7/z, [z31.d, #124]
+// CHECK-ENCODING: [0xff,0x9f,0x3f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 3f c5 <unknown>
+
+ld1sw { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1sw { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0x80,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 20 c5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -123,3 +123,57 @@ ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1w z0.s, p0/z, [z0.s, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [z0.s, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [z0.s, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.d, p0/z, [z0.d, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.d, p0/z, [z0.d, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.d, p0/z, [z0.d, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1w.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1w.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1w.s Sun Apr 29 10:33:38 2018
@@ -132,3 +132,27 @@ ld1w { z0.d }, p0/z, [x0, z0.d, sxtw
// CHECK-ENCODING: [0x00,0x40,0x60,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 60 c5 <unknown>
+
+ld1w { z31.s }, p7/z, [z31.s, #124]
+// CHECK-INST: ld1w { z31.s }, p7/z, [z31.s, #124]
+// CHECK-ENCODING: [0xff,0xdf,0x3f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 3f 85 <unknown>
+
+ld1w { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ld1w { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 20 85 <unknown>
+
+ld1w { z31.d }, p7/z, [z31.d, #124]
+// CHECK-INST: ld1w { z31.d }, p7/z, [z31.d, #124]
+// CHECK-ENCODING: [0xff,0xdf,0x3f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 3f c5 <unknown>
+
+ld1w { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1w { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 20 c5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1b-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1b-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -88,3 +88,27 @@ ldff1b z0.d, p0/z, [x0, z0.d, sxtw #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.d, sxtw #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1b z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1b z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1b z0.s, p0/z, [z0.s, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1b z0.s, p0/z, [z0.s, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1b z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1b z0.d, p0/z, [z0.d, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1b.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1b.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1b.s Sun Apr 29 10:33:38 2018
@@ -102,3 +102,27 @@ ldff1b { z21.d }, p5/z, [x10, z21.d, sx
// CHECK-ENCODING: [0x55,0x75,0x55,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 55 c4 <unknown>
+
+ldff1b { z31.s }, p7/z, [z31.s, #31]
+// CHECK-INST: ldff1b { z31.s }, p7/z, [z31.s, #31]
+// CHECK-ENCODING: [0xff,0xff,0x3f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 3f 84 <unknown>
+
+ldff1b { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ldff1b { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xe0,0x20,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 20 84 <unknown>
+
+ldff1b { z31.d }, p7/z, [z31.d, #31]
+// CHECK-INST: ldff1b { z31.d }, p7/z, [z31.d, #31]
+// CHECK-ENCODING: [0xff,0xff,0x3f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 3f c4 <unknown>
+
+ldff1b { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1b { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xe0,0x20,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 20 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -72,3 +72,42 @@ ldff1d z0.d, p0/z, [x0, z0.d, lsl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, lsl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1d z0.s, p0/z, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.s, p0/z, [z0.s, #8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s, #8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.d, p0/z, [z0.d, #-8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #-8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.d, p0/z, [z0.d, #249]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #249]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.d, p0/z, [z0.d, #256]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #256]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1d.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1d.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1d.s Sun Apr 29 10:33:38 2018
@@ -60,3 +60,15 @@ ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw
// CHECK-ENCODING: [0x00,0x60,0xe0,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 e0 c5 <unknown>
+
+ldff1d { z31.d }, p7/z, [z31.d, #248]
+// CHECK-INST: ldff1d { z31.d }, p7/z, [z31.d, #248]
+// CHECK-ENCODING: [0xff,0xff,0xbf,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff bf c5 <unknown>
+
+ldff1d { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1d { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xe0,0xa0,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 a0 c5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -87,3 +87,57 @@ ldff1h z0.d, p0/z, [x0, z0.d, sxtw #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.d, sxtw #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1h z0.s, p0/z, [z0.s, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.s, p0/z, [z0.s, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.s, p0/z, [z0.s, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.s, p0/z, [z0.s, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.s, p0/z, [z0.s, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.s, p0/z, [z0.s, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.d, p0/z, [z0.d, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.d, p0/z, [z0.d, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.d, p0/z, [z0.d, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1h.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1h.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1h.s Sun Apr 29 10:33:38 2018
@@ -120,3 +120,27 @@ ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw
// CHECK-ENCODING: [0x00,0x60,0xe0,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 e0 c4 <unknown>
+
+ldff1h { z31.s }, p7/z, [z31.s, #62]
+// CHECK-INST: ldff1h { z31.s }, p7/z, [z31.s, #62]
+// CHECK-ENCODING: [0xff,0xff,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff bf 84 <unknown>
+
+ldff1h { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ldff1h { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xe0,0xa0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 a0 84 <unknown>
+
+ldff1h { z31.d }, p7/z, [z31.d, #62]
+// CHECK-INST: ldff1h { z31.d }, p7/z, [z31.d, #62]
+// CHECK-ENCODING: [0xff,0xff,0xbf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff bf c4 <unknown>
+
+ldff1h { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1h { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xe0,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 a0 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sb-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sb-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sb-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -91,3 +91,27 @@ ldff1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1sb z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1sb z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sb z0.s, p0/z, [z0.s, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1sb z0.s, p0/z, [z0.s, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sb z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1sb z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sb z0.d, p0/z, [z0.d, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1sb z0.d, p0/z, [z0.d, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sb.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sb.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sb.s Sun Apr 29 10:33:38 2018
@@ -90,3 +90,27 @@ ldff1sb { z21.d }, p5/z, [x10, z21.d, sx
// CHECK-ENCODING: [0x55,0x35,0x55,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 35 55 c4 <unknown>
+
+ldff1sb { z31.s }, p7/z, [z31.s, #31]
+// CHECK-INST: ldff1sb { z31.s }, p7/z, [z31.s, #31]
+// CHECK-ENCODING: [0xff,0xbf,0x3f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 3f 84 <unknown>
+
+ldff1sb { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ldff1sb { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 84 <unknown>
+
+ldff1sb { z31.d }, p7/z, [z31.d, #31]
+// CHECK-INST: ldff1sb { z31.d }, p7/z, [z31.d, #31]
+// CHECK-ENCODING: [0xff,0xbf,0x3f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 3f c4 <unknown>
+
+ldff1sb { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1sb { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -81,3 +81,57 @@ ldff1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1sh z0.s, p0/z, [z0.s, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.s, p0/z, [z0.s, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.s, p0/z, [z0.s, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.s, p0/z, [z0.s, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.s, p0/z, [z0.s, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.s, p0/z, [z0.s, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.d, p0/z, [z0.d, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.d, p0/z, [z0.d, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.d, p0/z, [z0.d, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sh.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sh.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sh.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sh.s Sun Apr 29 10:33:38 2018
@@ -102,3 +102,27 @@ ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw
// CHECK-ENCODING: [0x00,0x20,0xe0,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 20 e0 c4 <unknown>
+
+ldff1sh { z31.s }, p7/z, [z31.s, #62]
+// CHECK-INST: ldff1sh { z31.s }, p7/z, [z31.s, #62]
+// CHECK-ENCODING: [0xff,0xbf,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf bf 84 <unknown>
+
+ldff1sh { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ldff1sh { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 84 <unknown>
+
+ldff1sh { z31.d }, p7/z, [z31.d, #62]
+// CHECK-INST: ldff1sh { z31.d }, p7/z, [z31.d, #62]
+// CHECK-ENCODING: [0xff,0xbf,0xbf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf bf c4 <unknown>
+
+ldff1sh { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1sh { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -82,3 +82,42 @@ ldff1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1sw z0.s, p0/z, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldff1sw z0.s, p0/z, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.s, p0/z, [z0.s, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldff1sw z0.s, p0/z, [z0.s, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.d, p0/z, [z0.d, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.d, p0/z, [z0.d, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.d, p0/z, [z0.d, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sw.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sw.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sw.s Sun Apr 29 10:33:38 2018
@@ -60,3 +60,15 @@ ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw
// CHECK-ENCODING: [0x00,0x20,0x60,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 20 60 c5 <unknown>
+
+ldff1sw { z31.d }, p7/z, [z31.d, #124]
+// CHECK-INST: ldff1sw { z31.d }, p7/z, [z31.d, #124]
+// CHECK-ENCODING: [0xff,0xbf,0x3f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 3f c5 <unknown>
+
+ldff1sw { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1sw { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 c5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s Sun Apr 29 10:33:38 2018
@@ -87,3 +87,57 @@ ldff1w z0.d, p0/z, [x0, z0.d, sxtw #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.d, sxtw #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1w z0.s, p0/z, [z0.s, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.s, p0/z, [z0.s, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.s, p0/z, [z0.s, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.s, p0/z, [z0.s, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.s, p0/z, [z0.s, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.s, p0/z, [z0.s, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.d, p0/z, [z0.d, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.d, p0/z, [z0.d, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.d, p0/z, [z0.d, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1w.s?rev=331145&r1=331144&r2=331145&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1w.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1w.s Sun Apr 29 10:33:38 2018
@@ -102,3 +102,27 @@ ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw
// CHECK-ENCODING: [0x00,0x60,0x60,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 60 c5 <unknown>
+
+ldff1w { z31.s }, p7/z, [z31.s, #124]
+// CHECK-INST: ldff1w { z31.s }, p7/z, [z31.s, #124]
+// CHECK-ENCODING: [0xff,0xff,0x3f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 3f 85 <unknown>
+
+ldff1w { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ldff1w { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xe0,0x20,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 20 85 <unknown>
+
+ldff1w { z31.d }, p7/z, [z31.d, #124]
+// CHECK-INST: ldff1w { z31.d }, p7/z, [z31.d, #124]
+// CHECK-ENCODING: [0xff,0xff,0x3f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 3f c5 <unknown>
+
+ldff1w { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1w { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xe0,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 20 c5 <unknown>
More information about the llvm-commits
mailing list