[llvm] r331138 - [X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add aliases based on 16/32-bit mode to choose the default.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 28 23:24:09 PDT 2018
Author: ctopper
Date: Sat Apr 28 23:24:09 2018
New Revision: 331138
URL: http://llvm.org/viewvc/llvm-project?rev=331138&view=rev
Log:
[X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add aliases based on 16/32-bit mode to choose the default.
This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size.
This matches gas behavior from what I could tell.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSystem.td
llvm/trunk/test/MC/Disassembler/X86/intel-syntax-32.txt
llvm/trunk/test/MC/X86/intel-syntax-ptr-sized.s
Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=331138&r1=331137&r2=331138&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Sat Apr 28 23:24:09 2018
@@ -359,15 +359,15 @@ def VERWm : I<0x00, MRM5m, (outs), (ins
let SchedRW = [WriteSystem] in {
def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
- "sgdt{w}\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
+ "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
- "sgdt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
+ "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
"sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
- "sidt{w}\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
+ "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
- "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
+ "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
"sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
@@ -384,15 +384,15 @@ def SLDT64r : RI<0x00, MRM0r, (outs GR64
"sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
- "lgdt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
+ "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
- "lgdt{l}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
+ "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
"lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
- "lidt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
+ "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
- "lidt{l}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
+ "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
"lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
@@ -402,6 +402,15 @@ def LLDT16m : I<0x00, MRM2m, (outs), (in
"lldt{w}\t$src", []>, TB;
} // SchedRW
+def : InstAlias<"sgdt\t$dst", (SGDT16m opaque48mem:$dst), 0>, Requires<[In16BitMode]>;
+def : InstAlias<"sgdt\t$dst", (SGDT32m opaque48mem:$dst), 0>, Requires<[In32BitMode]>;
+def : InstAlias<"sidt\t$dst", (SIDT16m opaque48mem:$dst), 0>, Requires<[In16BitMode]>;
+def : InstAlias<"sidt\t$dst", (SIDT32m opaque48mem:$dst), 0>, Requires<[In32BitMode]>;
+def : InstAlias<"lgdt\t$src", (LGDT16m opaque48mem:$src), 0>, Requires<[In16BitMode]>;
+def : InstAlias<"lgdt\t$src", (LGDT32m opaque48mem:$src), 0>, Requires<[In32BitMode]>;
+def : InstAlias<"lidt\t$src", (LIDT16m opaque48mem:$src), 0>, Requires<[In16BitMode]>;
+def : InstAlias<"lidt\t$src", (LIDT32m opaque48mem:$src), 0>, Requires<[In32BitMode]>;
+
//===----------------------------------------------------------------------===//
// Specialized register support
let SchedRW = [WriteSystem] in {
Modified: llvm/trunk/test/MC/Disassembler/X86/intel-syntax-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/intel-syntax-32.txt?rev=331138&r1=331137&r2=331138&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/intel-syntax-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/intel-syntax-32.txt Sat Apr 28 23:24:09 2018
@@ -1,15 +1,15 @@
# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s
-# CHECK: sgdt opaque ptr [eax]
+# CHECK: sgdtd opaque ptr [eax]
0x0f 0x01 0x00
-# CHECK: sidt opaque ptr [eax]
+# CHECK: sidtd opaque ptr [eax]
0x0f 0x01 0x08
-# CHECK: lgdt opaque ptr [eax]
+# CHECK: lgdtd opaque ptr [eax]
0x0f 0x01 0x10
-# CHECK: lidt opaque ptr [eax]
+# CHECK: lidtd opaque ptr [eax]
0x0f 0x01 0x18
# CHECK: mov al, byte ptr [878082192]
Modified: llvm/trunk/test/MC/X86/intel-syntax-ptr-sized.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/intel-syntax-ptr-sized.s?rev=331138&r1=331137&r2=331138&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/intel-syntax-ptr-sized.s (original)
+++ llvm/trunk/test/MC/X86/intel-syntax-ptr-sized.s Sat Apr 28 23:24:09 2018
@@ -9,6 +9,15 @@ call [eax]
jmp [eax]
// CHECK: jmpl *(%eax)
+lgdt [eax]
+// CHECK: lgdtl (%eax)
+lidt [eax]
+// CHECK: lidtl (%eax)
+sgdt [eax]
+// CHECK: sgdtl (%eax)
+sidt [eax]
+// CHECK: sidtl (%eax)
+
// mode switch
.code16
@@ -18,3 +27,12 @@ call [eax]
// CHECK: callw *(%eax)
jmp [eax]
// CHECK: jmpw *(%eax)
+
+lgdt [eax]
+// CHECK: lgdtw (%eax)
+lidt [eax]
+// CHECK: lidtw (%eax)
+sgdt [eax]
+// CHECK: sgdtw (%eax)
+sidt [eax]
+// CHECK: sidtw (%eax)
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